+2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (neg): New instruction variant.
+
+2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-dis.c (find_format, find_format, get_auxreg)
+ (print_insn_arc): Changed.
+ * arc-ext.h (INSERT_XOP): Likewise.
+
+2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * tic54x-dis.c (sprint_mmr): Adjust.
+ * tic54x-opc.c: Likewise.
+
+2016-05-19 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
+
+2016-05-19 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c: Formatting.
+ (NSISIGNOPT): Define.
+ (powerpc_opcodes <subis>): Use NSISIGNOPT.
+
+2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
+ replacing references to `micromips_ase' throughout.
+ (_print_insn_mips): Don't use file-level microMIPS annotation to
+ determine the disassembly mode with the symbol table.
+
+2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
+
+2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
+ mips64r6.
+ * mips-opc.c (D34): New macro.
+ (mips_builtin_opcodes): Define bposge32c for DSPr3.
+
+2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
+
+ * i386-dis.c (prefix_table): Add RDPID instruction.
+ * i386-gen.c (cpu_flag_init): Add RDPID flag.
+ (cpu_flags): Add RDPID bitfield.
+ * i386-opc.h (enum): Add RDPID element.
+ (i386_cpu_flags): Add RDPID field.
+ * i386-opc.tbl: Add RDPID instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Regenerate.
+
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
+ branch type of a symbol.
+ (print_insn): Likewise.
+
+2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
+ Mainline Security Extensions instructions.
+ (thumb_opcodes): Add entries for narrow ARMv8-M Security
+ Extensions instructions.
+ (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
+ instructions.
+ (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
+ special registers.
+
+2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
+
+2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
+ (arcExtMap_genOpcode): Likewise.
+ * arc-opc.c (arg_32bit_rc): Define new variable.
+ (arg_32bit_u6): Likewise.
+ (arg_32bit_limm): Likewise.
+
+2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-gen.c (VERIFIER): Define.
+ * aarch64-opc.c (VERIFIER): Define.
+ (verify_ldpsw): Use static linkage.
+ * aarch64-opc.h (verify_ldpsw): Remove.
+ * aarch64-tbl.h: Use VERIFIER for verifiers.
+
+2016-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR target/19722
+ * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
+ * aarch64-opc.c (verify_ldpsw): New function.
+ * aarch64-opc.h (verify_ldpsw): New prototype.
+ * aarch64-tbl.h: Add initialiser for verifier field.
+ (LDPSW): Set verifier to verify_ldpsw.
+
+2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/19983
+ PR binutils/19984
+ * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
+ smaller than address size.
+
+2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * alpha-dis.c: Regenerate.
+ * crx-dis.c: Likewise.
+ * disassemble.c: Likewise.
+ * epiphany-opc.c: Likewise.
+ * fr30-opc.c: Likewise.
+ * frv-opc.c: Likewise.
+ * ip2k-opc.c: Likewise.
+ * iq2000-opc.c: Likewise.
+ * lm32-opc.c: Likewise.
+ * lm32-opinst.c: Likewise.
+ * m32c-opc.c: Likewise.
+ * m32r-opc.c: Likewise.
+ * m32r-opinst.c: Likewise.
+ * mep-opc.c: Likewise.
+ * mt-opc.c: Likewise.
+ * or1k-opc.c: Likewise.
+ * or1k-opinst.c: Likewise.
+ * tic80-opc.c: Likewise.
+ * xc16x-opc.c: Likewise.
+ * xstormy16-opc.c: Likewise.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
+ fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
+ calcsd, and calcxd instructions.
+ * arc-opc.c (insert_nps_bitop_size): Delete.
+ (extract_nps_bitop_size): Delete.
+ (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
+ (extract_nps_qcmp_m3): Define.
+ (extract_nps_qcmp_m2): Define.
+ (extract_nps_qcmp_m1): Define.
+ (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
+ (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
+ (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
+ NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
+ NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
+ NPS_QCMP_M3.
+
+2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
+
+2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.in: Regenerated with automake 1.11.6.
+ * aclocal.m4: Likewise.
+
+2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
+ instructions.
+ * arc-opc.c (insert_nps_cmem_uimm16): New function.
+ (extract_nps_cmem_uimm16): New function.
+ (arc_operands): Add NPS_XLDST_UIMM16 operand.
+
+2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (arc_insn_length): New function.
+ (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
+ (find_format): Change insnLen parameter to unsigned.
+
+2016-04-13 Nick Clifton <nickc@redhat.com>
+
+ PR target/19937
+ * v850-opc.c (v850_opcodes): Correct masks for long versions of
+ the LD.B and LD.BU instructions.
+
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (find_format): Check for extension flags.
+ (print_flags): New function.
+ (print_insn_arc): Update for .extCondCode, .extCoreRegister and
+ .extAuxRegister.
+ * arc-ext.c (arcExtMap_coreRegName): Use
+ LAST_EXTENSION_CORE_REGISTER.
+ (arcExtMap_coreReadWrite): Likewise.
+ (dump_ARC_extmap): Update printing.
+ * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
+ (arc_aux_regs): Add cpu field.
+ * arc-regs.h: Add cpu field, lower case name aux registers.
+
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h: Add rtsc, sleep with no arguments.
+
+2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
+ Initialize.
+ (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
+ (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
+ (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
+ (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
+ (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
+ (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
+ (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
+ (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
+ (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
+ (arc_opcode arc_opcodes): Null terminate the array.
+ (arc_num_opcodes): Remove.
+ * arc-ext.h (INSERT_XOP): Define.
+ (extInstruction_t): Likewise.
+ (arcExtMap_instName): Delete.
+ (arcExtMap_insn): New function.
+ (arcExtMap_genOpcode): Likewise.
+ * arc-ext.c (ExtInstruction): Remove.
+ (create_map): Zero initialize instruction fields.
+ (arcExtMap_instName): Remove.
+ (arcExtMap_insn): New function.
+ (dump_ARC_extmap): More info while debuging.
+ (arcExtMap_genOpcode): New function.
+ * arc-dis.c (find_format): New function.
+ (print_insn_arc): Use find_format.
+ (arc_get_disassembler): Enable dump_ARC_extmap only when
+ debugging.
+
+2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Mask unused extended
+ instruction bits out.
+
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
+ * arc-opc.c (arc_flag_operands): Add new flags.
+ (arc_flag_classes): Add new classes.
+
+2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
+
+2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
+ encode1, rflt, crc16, and crc32 instructions.
+ * arc-opc.c (arc_flag_operands): Add F_NPS_R.
+ (arc_flag_classes): Add C_NPS_R.
+ (insert_nps_bitop_size_2b): New function.
+ (extract_nps_bitop_size_2b): Likewise.
+ (insert_nps_bitop_uimm8): Likewise.
+ (extract_nps_bitop_uimm8): Likewise.
+ (arc_operands): Add new operand entries.
+
+2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h: Add a new subclass field. Add double assist
+ accumulator register values.
+ * arc-tbl.h: Use DPA subclass to mark the double assist
+ instructions. Use DPX/SPX subclas to mark the FPX instructions.
+ * arc-opc.c (RSP): Define instead of SP.
+ (arc_aux_regs): Add the subclass field.
+
+2016-04-05 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
+
+2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
+ NPS_R_SRC1.
+
+2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
+ issues. No functional changes.
+
+2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
+ (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
+ (RTT): Remove duplicate.
+ (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
+ (PCT_CONFIG*): Remove.
+ (D1L, D1H, D2H, D2L): Define.
+
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
+
+2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (invld07): Remove.
+ * arc-ext-tbl.h: New file.
+ * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
+ * arc-opc.c (arc_opcodes): Add ext-tbl include.
+
+2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
+
+ Fix -Wstack-usage warnings.
+ * aarch64-dis.c (print_operands): Substitute size.
+ * aarch64-opc.c (print_register_offset_address): Substitute tblen.
+
+2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
+ to get a proper diagnostic when an invalid ASR register is used.
+
+2016-03-22 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: New file.
+ * arc-opc.c: Add top level comment.
+ (insert_nps_3bit_dst): New function.
+ (extract_nps_3bit_dst): New function.
+ (insert_nps_3bit_src2): New function.
+ (extract_nps_3bit_src2): New function.
+ (insert_nps_bitop_size): New function.
+ (extract_nps_bitop_size): New function.
+ (arc_flag_operands): Add nps400 entries.
+ (arc_flag_classes): Add nps400 entries.
+ (arc_operands): Add nps400 entries.
+ (arc_opcodes): Add nps400 include.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_flag_classes): Convert all flag classes to use
+ the new class enum values.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (print_insn_arc): Handle nps400.
+
+2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (BASE): Delete.
+
+2016-03-18 Nick Clifton <nickc@redhat.com>
+
+ PR target/19721
+ * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
+ of MOV insn that aliases an ORR insn.
+
+2016-03-16 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (neon_opcodes): Support new FP16 instructions.
+
+2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
+
+ * mcore-opc.h: Add const qualifiers.
+ * microblaze-opc.h (struct op_code_struct): Likewise.
+ * sh-opc.h: Likewise.
+ * tic4x-dis.c (tic4x_print_indirect): Likewise.
+ (tic4x_print_op): Likewise.
+
+2016-03-02 Alan Modra <amodra@gmail.com>
+
+ * or1k-desc.h: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * rl78-decode.c: Regenerate.
+
+2016-03-01 Nick Clifton <nickc@redhat.com>
+
+ PR target/19747
+ * rl78-dis.c (print_insn_rl78_common): Fix typo.
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
+ (print_insn_coprocessor): Support fp16 instructions.
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
+ vminnm, vrint(mpna).
+
+2016-02-24 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor): Check co-processor number for
+ cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
+
+2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (print_insn): Parenthesize expression to prevent
+ truncated addresses.
+ (OP_J): Likewise.
+
+2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
+ Janek van Oirschot <jvanoirs@synopsys.com>
+
+ * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
+ variable.
+
+2016-02-04 Nick Clifton <nickc@redhat.com>
+
+ PR target/19561
+ * msp430-dis.c (print_insn_msp430): Add a special case for
+ decoding an RRC instruction with the ZC bit set in the extension
+ word.
+
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * cgen-ibld.in (insert_normal): Rework calculation of shift.
+ * epiphany-ibld.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+
+2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * epiphany-dis.c: Regenerated from latest cpu files.
+
+2016-02-01 Michael McConville <mmcco@mykolab.com>
+
+ * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
+ test bit.
+
+2016-01-25 Renlin Li <renlin.li@arm.com>
+
+ * arm-dis.c (mapping_symbol_for_insn): New function.
+ (find_ifthen_state): Call mapping_symbol_for_insn().
+
+2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Check validity
+ of MSR UAO immediate operand.
+
+2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
+ instruction support.
+
+2016-01-17 Alan Modra <amodra@gmail.com>
+
+ * configure: Regenerate.
+
+2016-01-14 Nick Clifton <nickc@redhat.com>
+
+ * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
+ instructions that can support stack pointer operations.
+ * rl78-decode.c: Regenerate.
+ * rl78-dis.c: Fix display of stack pointer in MOVW based
+ instructions.
+
+2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
+ testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
+ erxtatus_el1 and erxaddr_el1.
+
+2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add "esb".
+ (thumb_opcodes): Likewise.
+
+2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c <xscmpnedp>: Delete.
+ <xvcmpnedp>: Likewise.
+ <xvcmpnedp.>: Likewise.
+ <xvcmpnesp>: Likewise.
+ <xvcmpnesp.>: Likewise.
+
+2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
+
+ PR gas/13050
+ * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
+ addition to ISA_A.
+
+2016-01-01 Alan Modra <amodra@gmail.com>
+
+ Update year range in copyright notice of all files.
+
For older changes see ChangeLog-2015
\f
Copyright (C) 2016 Free Software Foundation, Inc.
projects / deliverable / binutils-gdb.git / blobdiff