[AArch64][PATCH 5/14] Support FP16 Scalar Two Register Misc. instructions.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3e9908c660b104d5b3c33287874911567323e5c9..5993ba5538b175e3e88d84c7fda56f1beabbccb4 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,15 @@
+2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc-2.c: Regenerate.
+       * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
+       (QL_S_2SAMEH): New.
+       (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
+       fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
+       frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
+       fcvtzu and frsqrte to the scalar two register misc. group.
+
 2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>
 
        * aarch64-asm-2.c: Regenerate.