+Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
+
+start-sanitize-tic80
+Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8.
+
+Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Define r25 properly.
+
+end-sanitize-tic80
+Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
+ floatformat_to_double to make portable.
+ (print_insn_arg): Use NEXTEXTEND macro when extracting extended
+ precision float.
+
+Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes,
+ and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes.
+
+Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+start-sanitize-tic80
+Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (LSI_SCALED): Renamed from this ...
+ (OFF_SL_BR_SCALED): ... to this, and added the flag
+ TIC80_OPERAND_BASEREL to the flags word.
+ (tic80_opcodes): Replace all occurances of LSI_SCALED with
+ OFF_SL_BR_SCALED.
+
+end-sanitize-tic80
+Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
+ Change mips_opcodes from const array to a pointer,
+ and change bfd_mips_num_opcodes from const int to int,
+ so that we can increase the size of the mips opcodes table
+ dynamically.
+
+start-sanitize-tic80
+Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Revert change to
+ store BITNUM values in the table in one's complement form
+ to match behavior when assembler is given a raw numeric
+ value for a BITNUM operand.
+ * tic80-dis.c (print_operand_bitnum): Ditto.
+
+end-sanitize-tic80
+start-sanitize-d30v
+Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d30v-opc.c: Removed references to FLAG_X.
+
+end-sanitize-d30v
+Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in: Add dependencies on ../bfd/bfd.h as required.
+
+start-sanitize-d30v
+Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * Makefile.in: Added d30v object files.
+ * configure: (bfd_d30v_arch) Rebuilt.
+ * configure.in: (bfd_d30v_arch) Added new case.
+ * d30v-dis.c: New file.
+ * d30v-opc.c: New file.
+ * disassemble.c (disassembler) Add entry for d30v.
+
+end-sanitize-d30v
+start-sanitize-tic80
+Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ representations for the floating point BITNUM values.
+
+Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values
+ in the table in one's complement form, as they appear in the
+ actual instruction.
+ (tic80_symbol_to_value): Use macros to access predefined
+ symbol fields.
+ (tic80_value_to_symbol): Ditto.
+ (tic80_next_predefined_symbol): New function.
+ * tic80-dis.c (print_operand_bitnum): Remove code that did
+ one's complement for BITNUM values.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Fri Feb 14 13:56:51 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: bug fix, can't mark insns INSN_5900 and INSN_ISA4
+
+end-sanitize-r5900
+Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de>
+
+ * makefile.vms: Remove 8 bit characters. Update to latest
+ gcc release.
+
+Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
+
+Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (IMM16_PCREL): This is a signed operand.
+ (IMM24_PCREL): Likewise.
+
+Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base
+ address for an extended PC relative instruction that is not a
+ branch.
+
+Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
+ bytes_per_line.
+
+start-sanitize-tic80
+Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
+ (tic80_opcodes): Sort entries so that long immediate forms
+ come after short immediate forms, making it easier for
+ assembler to select the right one for a given operand.
+
+end-sanitize-tic80
+Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and
+ display_endian.
+ (print_insn_mips16): Likewise.
+
+start-sanitize-r5900
+Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: add r5900.
+
+end-sanitize-r5900
+start-sanitize-tic80
+Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_symbol_to_value): Changed to accept
+ a symbol class that restricts translation to just that
+ class (general register, condition code, etc).
+
+Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
+ and REG_DEST_E for register operands that have to be
+ an even numbered register. Add REG_FPA for operands that
+ are one of the floating point accumulator registers.
+ Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
+ (tic80_opcodes): Change entries that need even numbered
+ register operands to use the new operand table entries.
+ Add "or" entries that are identical to "or.tt" entries.
+
+end-sanitize-tic80
+Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Add new cases of exit instruction for
+ disassembler.
+ * mips-dis.c (print_mips16_insn_arg): Display floating point
+ registers in operands of exit instruction. Print `$' before
+ register names in operands of entry and exit instructions.
+
+start-sanitize-tic80
+Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Table of name/value
+ pairs for all predefined symbols recognized by the assembler.
+ Also used by the disassembling routines.
+ (tic80_symbol_to_value): New function.
+ (tic80_value_to_symbol): New function.
+ * tic80-dis.c (print_operand_control_register,
+ print_operand_condition_code, print_operand_bitnum):
+ Remove private tables and use tic80_value_to_symbol function.
+
+end-sanitize-tic80
+Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c (print_operand): Change address printing
+ to correctly handle PC wrapping. Fixes PR11490.
+
+Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
+ branchs relaxable.
+
Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com>
* mips-dis.c (print_insn_mips16): Set insn_info information.
* tic80-opc.c: Add file.
end-sanitize-tic80
-start-sanitize-d10v
Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
-end-sanitize-d10v
Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com)
* mn10200-opc.c (mn10200_operands): Add SIMM16N.
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-start-sanitize-d10v
Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
-end-sanitize-d10v
Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_opcodes): Demand parens around
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
-start-sanitize-d10v
Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
sequential so the assembler never parallelizes it with
other instructions.
-end-sanitize-d10v
Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
end of the opcode table.
end-sanitize-v850
-start-sanitize-d10v
Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Added register pairs,
"r0-r1", "r2-r3", etc.
-end-sanitize-d10v
start-sanitize-v850
Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
-start-sanitize-d10v
Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c: Add additional information to the opcode
table to help determinine which instructions can be done
in parallel.
-end-sanitize-d10v
Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com>
* mpw-make.sed: Update editing of include pathnames to be
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
-start-sanitize-d10v
Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
-end-sanitize-d10v
Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>
* makefile.vms: Update for alpha-opc changes.
* i386-dis.c (print_insn_i386): Actually return the correct value.
(ONE, OP_ONE): #ifdef out; not used.
-start-sanitize-d10v
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
-end-sanitize-d10v
Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
-start-sanitize-d10v
Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
-end-sanitize-d10v
Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com>
* alpha-dis.c (print_insn_alpha_osf): Remove.
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
-start-sanitize-d10v
Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-dis.c (dis_long): Handle unknown opcodes.
* d10v-dis.c: Change all functions to use info->print_address_func.
-end-sanitize-d10v
Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
-start-sanitize-d10v
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
-end-sanitize-d10v
Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com>
* sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
* configure: Rebuild.
* Makefile.in (install): Use @INSTALL_SHLIB@.
-start-sanitize-d10v
- Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* configure: (bfd_d10v_arch) Add new case.
* configure.in: (bfd_d10v_arch) Add new case.
* d10v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d10v.
-end-sanitize-d10v
Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com>
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
projects / deliverable / binutils-gdb.git / blobdiff