+Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
+
+start-sanitize-tic80
+Thu Feb 27 11:36:41 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Set info->bytes_per_line to 8.
+
+Wed Feb 26 15:34:48 1997 Michael Meissner <meissner@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Define r25 properly.
+
+end-sanitize-tic80
+Wed Feb 26 13:38:30 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (NEXTSINGLE, NEXTDOUBLE, NEXTEXTEND): Use
+ floatformat_to_double to make portable.
+ (print_insn_arg): Use NEXTEXTEND macro when extracting extended
+ precision float.
+
+Mon Feb 24 19:26:12 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Initialize mips_opcodes to mips_builtin_opcodes,
+ and bfd_mips_num_opcodes to bfd_mips_num_builtin_opcodes.
+
+Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
+
+start-sanitize-tic80
+Mon Feb 24 14:33:26 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (LSI_SCALED): Renamed from this ...
+ (OFF_SL_BR_SCALED): ... to this, and added the flag
+ TIC80_OPERAND_BASEREL to the flags word.
+ (tic80_opcodes): Replace all occurances of LSI_SCALED with
+ OFF_SL_BR_SCALED.
+
+end-sanitize-tic80
+Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
+
+ * mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
+ Change mips_opcodes from const array to a pointer,
+ and change bfd_mips_num_opcodes from const int to int,
+ so that we can increase the size of the mips opcodes table
+ dynamically.
+
+start-sanitize-tic80
+Sat Feb 22 21:03:47 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Revert change to
+ store BITNUM values in the table in one's complement form
+ to match behavior when assembler is given a raw numeric
+ value for a BITNUM operand.
+ * tic80-dis.c (print_operand_bitnum): Ditto.
+
+end-sanitize-tic80
+start-sanitize-d30v
+Fri Feb 21 16:31:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d30v-opc.c: Removed references to FLAG_X.
+
+end-sanitize-d30v
+Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in: Add dependencies on ../bfd/bfd.h as required.
+
+start-sanitize-d30v
+Tue Feb 18 17:43:43 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * Makefile.in: Added d30v object files.
+ * configure: (bfd_d30v_arch) Rebuilt.
+ * configure.in: (bfd_d30v_arch) Added new case.
+ * d30v-dis.c: New file.
+ * d30v-opc.c: New file.
+ * disassemble.c (disassembler) Add entry for d30v.
+
+end-sanitize-d30v
+start-sanitize-tic80
+Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ representations for the floating point BITNUM values.
+
+Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Store BITNUM values
+ in the table in one's complement form, as they appear in the
+ actual instruction.
+ (tic80_symbol_to_value): Use macros to access predefined
+ symbol fields.
+ (tic80_value_to_symbol): Ditto.
+ (tic80_next_predefined_symbol): New function.
+ * tic80-dis.c (print_operand_bitnum): Remove code that did
+ one's complement for BITNUM values.
+
+end-sanitize-tic80
+start-sanitize-r5900
+Fri Feb 14 13:56:51 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: bug fix, can't mark insns INSN_5900 and INSN_ISA4
+
+end-sanitize-r5900
+Thu Feb 13 21:56:51 1997 Klaus Kaempf <kkaempf@progis.de>
+
+ * makefile.vms: Remove 8 bit characters. Update to latest
+ gcc release.
+
+Thu Feb 13 20:41:22 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
+
+ * m68k-opc.c (m68k_opcodes): Add swbeg pseudo-instruction.
+
+Thu Feb 13 16:30:02 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (IMM16_PCREL): This is a signed operand.
+ (IMM24_PCREL): Likewise.
+
+Thu Feb 13 13:28:43 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Use memaddr - 2 as the base
+ address for an extended PC relative instruction that is not a
+ branch.
+
+Wed Feb 12 12:27:40 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c (print_insn_m68k): Set bytes_per_chunk and
+ bytes_per_line.
+
+start-sanitize-tic80
+Tue Feb 11 16:36:31 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Fix typo '+' -> '|'.
+ (tic80_opcodes): Sort entries so that long immediate forms
+ come after short immediate forms, making it easier for
+ assembler to select the right one for a given operand.
+
+end-sanitize-tic80
+Tue Feb 11 15:26:47 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Set bytes_per_chunk and
+ display_endian.
+ (print_insn_mips16): Likewise.
+
+start-sanitize-r5900
+Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips-opc.c: add r5900.
+
+end-sanitize-r5900
+start-sanitize-tic80
+Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_symbol_to_value): Changed to accept
+ a symbol class that restricts translation to just that
+ class (general register, condition code, etc).
+
+Thu Feb 6 17:34:09 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Add REG_0_E, REG_22_E,
+ and REG_DEST_E for register operands that have to be
+ an even numbered register. Add REG_FPA for operands that
+ are one of the floating point accumulator registers.
+ Add TIC80_OPERAND_MASK to flags for ENDMASK operand.
+ (tic80_opcodes): Change entries that need even numbered
+ register operands to use the new operand table entries.
+ Add "or" entries that are identical to "or.tt" entries.
+
+end-sanitize-tic80
+Wed Feb 5 11:12:44 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Add new cases of exit instruction for
+ disassembler.
+ * mips-dis.c (print_mips16_insn_arg): Display floating point
+ registers in operands of exit instruction. Print `$' before
+ register names in operands of entry and exit instructions.
+
+start-sanitize-tic80
+Thu Jan 30 14:09:03 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_predefined_symbols): Table of name/value
+ pairs for all predefined symbols recognized by the assembler.
+ Also used by the disassembling routines.
+ (tic80_symbol_to_value): New function.
+ (tic80_value_to_symbol): New function.
+ * tic80-dis.c (print_operand_control_register,
+ print_operand_condition_code, print_operand_bitnum):
+ Remove private tables and use tic80_value_to_symbol function.
+
+end-sanitize-tic80
+Thu Jan 30 11:30:45 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-dis.c (print_operand): Change address printing
+ to correctly handle PC wrapping. Fixes PR11490.
+
+Wed Jan 29 09:39:17 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_operands): Make 8 and 16 bit pc-relative
+ branchs relaxable.
+
+Tue Jan 28 15:57:34 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_insn_mips16): Set insn_info information.
+ (print_mips16_insn_arg): Likewise.
+
+ * mips-dis.c (print_insn_mips16): Better handling of an extend
+ opcode followed by an instruction which can not be extended.
+
+Fri Jan 24 12:08:21 1997 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Changed operand specifier for the
+ coldfire moveb instruction to not allow an address register as
+ destination. Although the documentation does not indicate that
+ this is invalid, experiments uncovered unexpected behavior.
+ Added a comment explaining the situation. Thanks to Andreas
+ Schwab for pointing this out to me.
+
+start-sanitize-tic80
+Wed Jan 22 20:13:51 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_opcodes): Expand comment to note that the
+ entries are presorted so that entries with the same mnemonic are
+ adjacent to each other in the table. Sort the entries for each
+ instruction so that this is true.
+
+end-sanitize-tic80
+Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-dis.c: Include <libiberty.h>.
+ (print_insn_m68k): Sort the opcode table on the most significant
+ nibble of the opcode.
+
+start-sanitize-tic80
+Sat Jan 18 15:15:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (tic80_opcodes): Add "wrcr", "vmpy", "vrnd",
+ "vsub", "vst", "xnor", and "xor" instructions.
+ (V_a1): Renamed from V_a, msb of accumulator reg number.
+ (V_a0): Add macro, lsb of accumulator reg number.
+
+Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Broke excessively long
+ function up into several smaller ones and arranged for
+ the instruction printing function to be callable recursively
+ to print vector instructions that have both a load and a
+ math instruction packed into a single opcode.
+ * tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
+ to explain why it comes after the other vector opcodes.
+
+end-sanitize-tic80
+Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
+ move insns to handle immediate operands.
+
+Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
+ fix operand mask in the "moveml" entries for the coldfire.
+
+start-sanitize-tic80
+Thu Jan 16 20:54:40 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (V_a, V_m, V_S, V_Z, V_p, OP_V, MASK_V):
+ New macros for building vector instruction opcodes.
+ (tic80_opcodes): Remove all uses of FMT_SI, FMT_REG, and
+ FMT_LI, which were unused. The field is now a flags field.
+ Remove some opcodes that are possible, but illegal, such
+ as long immediate instructions with doubles for immediate
+ values. Add "vadd" and "vld" instructions.
+
+Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (tic80_operands): Reorder some table entries to make
+ the order more logical. Move the shift alias instructions ("rotl",
+ "shl", "ins", "rotr", "extu", "exts", "srl", and "sra" to be
+ interspersed with the regular sr.x and sl.x instructions. Add
+ and test new instruction opcodes for "sl", "sli", "sr", "sri", "st",
+ "sub", "subu", "swcr", and "trap".
+
+Tue Jan 14 19:42:50 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-opc.c (OFF_SS_PC): Renamed from OFF_SS.
+ (OFF_SL_PC): Renamed from OFF_SL.
+ (OFF_SS_BR): New operand type for base relative operand.
+ (OFF_SL_BR): New operand type for base relative operand.
+ (REG_BASE): New operand type for base register operand.
+ (tic80_opcodes): Add and test "fmpy", "frndm", "frndn", "frndp",
+ "frndz", "fsqrt", "fsub", "illop0", "illopF", "ins", "jsr",
+ "ld", "ld.u", "lmo", "or", "rdcr", "rmo", "rotl", and "rotr"
+ instructions.
+ * tic80-dis.c (print_insn_tic80): Print opcode name with fixed width
+ 10 char field, padded with spaces on rhs, rather than a string
+ followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
+ than old TIC80_OPERAND_RELATIVE. Add support for new
+ TIC80_OPERAND_BASEREL flag bit.
+
+Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Print floating point operands
+ as floats.
+ * tic80-opc.c (SPFI): Add single precision floating point
+ immediate operand type.
+ (ROTATE): Add rotate operand type for shifts.
+ (ENDMASK): Add for shifts.
+ (n): Macro for the 'n' bit.
+ (i): Macro for the 'i' bit.
+ (PD): Macro for the 'PD' field.
+ (P2): Macro for the 'P2' field.
+ (P1): Macro for the 'P1' field.
+ (tic80_opcodes): Add entries for "exts", "extu", "fadd",
+ "fcmp", and "fdiv".
+
+end-sanitize-tic80
+Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c (disassemble): Mask off unwanted bits after
+ adding in current address for pc-relative operands.
+
+start-sanitize-tic80
+Mon Jan 6 10:56:25 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (R_SCALED): Add macro to test for ":s" modifier bit.
+ (print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
+ * tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
+ changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
+ (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
+ REG_BASE_M_SI, REG_BASE_M_LI respectively.
+ (REG_SCALED, LSI_SCALED): New operand types.
+ (E): New macro for 'E' bit at bit 27.
+ (tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
+ opcodes, including the various size flavors (b,h,w,d) for
+ the direct load and store instructions.
+
+Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
+ in an instruction.
+ * tic80-dis.c (print_insn_tic80): Change comma and paren handling.
+ Use M_SI and M_LI macros to check for ":m" modifier for GPR operands.
+ * tic80-opc.c (tic80_operands): Add REGM_SI and REGM_LI operands.
+ (F, M_REG, M_LI, M_SI, SZ_REG, SZ_LI, SZ_SI, D, S): New bit-twiddlers.
+ (MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
+ masks with "MASK_* & ~M_*" to get the M bit reset.
+ (tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
+
+Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com>
+
+ * tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
+ correctly. Add support for printing TIC80_OPERAND_BITNUM and
+ TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
+ form.
+ * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
+ CC, SICR, and LICR table entries.
+ (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
+ "bcnd", and "brcr" opcodes.
+
+end-sanitize-tic80
+Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com>
+
+ * ppc-opc.c (powerpc_operands): Make comment match the
+ actual fields (no shift field).
+ * sparc-opc.c (sparc_opcodes): Document why this cannot be "const".
+start-sanitize-tic80
+ * tic80-dis.c (print_insn_tic80): Replace abort stub with a
+ partial implementation, work in progress.
+ * tic80-opc.c (tic80_operands): Begin construction operands table.
+ (tic80_opcodes): Continue populating opcodes table and start
+ filling in the operand indices.
+ (tic80_num_opcodes): Add this.
+end-sanitize-tic80
+
+Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add #B case for moveq.
+
+Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disassemble): Make sure all variables are initialized
+ before they are used.
+
+start-sanitize-v850
+Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_opcodes): Put curly-braces around operands
+ for "breakpoint" instruction.
+
+end-sanitize-v850
+Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
+ (dep): Use ALL_CFLAGS rather than CFLAGS.
+
+start-sanitize-v850
+Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com>
+
+ * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY
+ flag.
+
+end-sanitize-v850
+Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com>
+
+ * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
+start-sanitize-tic80
+ (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
+end-sanitize-tic80
+
+Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Add "abs".
+
+start-sanitize-tic80
+Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com>
+
+ * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
+ * disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
+ (disassembler): Add bfd_arch_tic80 support to set disassemble
+ to print_insn_tic80.
+ * tic80-dis.c (print_insn_tic80): Add stub.
+
+Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com>
+
+ * configure.in (arch in $selarchs): Add bfd_tic80_arch entry.
+ * configure: Regenerate with autoconf.
+ * tic80-dis.c: Add file.
+ * tic80-opc.c: Add file.
+
+end-sanitize-tic80
+Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
+
+Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_operands): Add SIMM16N.
+ (mn10200_opcodes): Use it for some logicals and btst insns.
+ Add "break" and "trap" instructions.
+
+ * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
+
+ * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".
+
+Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): The base address of a PC
+ relative load or add now depends upon whether the instruction is
+ in a delay slot.
+
+Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c: Finish writing disassembler.
+ * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
+ Fix mask for "jmp (an)".
+
+ * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently
+ handle endianness issues for mn10300.
+
+ * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".
+
+Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
+ instruction. Fix opcode field for "movb (imm24),dn".
+
+ * mn10200-opc.c (mn10200_operands): Fix insertion position
+ for DI operand.
+
+Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c: Create mn10200 opcode table.
+ * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready,
+ but moving along nicely.
+
+Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de)
+
+ * Makefile.in (ALL_MACHINES): Add mips16-opc.o.
+
+Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Revert change to use < and >
+ specifiers for fmovem* instructions.
+
+Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disassemble): Remove '$' register prefixing.
+
+Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Change opcode for entry/exit to avoid conflicting
+ with dsrl.
+
+Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c: Add some comments explaining the various
+ operands and such.
+
+ * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
+
+Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * m68k-dis.c (print_insn_arg): Handle new < and > operand
+ specifiers.
+
+ * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
+ operand specifiers in fmovm* instructions.
+
+Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * ppc-opc.c (insert_li): Give an error if the offset has the two
+ least significant bits set.
+
+Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_insn_mips16): Separate the instruction from
+ the arguments with a tab, not a space.
+
+Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disasemble): Finish conversion to '$' as
+ register prefix.
+
+ * mn10300-opc.c (mn10300_opcodes): Fix mask field for
+ mov am,(imm32,sp).
+
+Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure: Rebuild with autoconf 2.12.
+
+ Add support for mips16 (16 bit MIPS implementation):
+ * mips16-opc.c: New file.
+ * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
+ (mips16_reg_names): New static array.
+ (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
+ after seeing a 16 bit symbol.
+ (print_insn_little_mips): Likewise.
+ (print_insn_mips16): New static function.
+ (print_mips16_insn_arg): New static function.
+ * mips-opc.c: Add jalx instruction.
+ * Makefile.in (mips16-opc.o): New target.
+ * configure.in: Use mips16-opc.o for bfd_mips_arch.
+ * configure: Rebuild.
+
Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com>
- * m68k-opc.c (m68k-opcodes): Fix many forms of the move
- instruction for the coldfire.
+ * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
+ operand specifiers in *save, *restore and movem* instructions.
+
+ * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
+ the coldfire.
- * m68k-opc.c (m68k-opcodes): The coldfire (mcf5200) can only use
+ * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-start-sanitize-d10v
Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
-end-sanitize-d10v
Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_opcodes): Demand parens around
the extended part of an instruction.
(mn10300_operands): Use new opcodes as appropriate.
-start-sanitize-d10v
Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
sequential so the assembler never parallelizes it with
other instructions.
-end-sanitize-d10v
Mon Nov 4 12:50:40 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for
end of the opcode table.
end-sanitize-v850
-start-sanitize-d10v
Mon Aug 26 13:35:53 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Added register pairs,
"r0-r1", "r2-r3", etc.
-end-sanitize-d10v
start-sanitize-v850
Fri Aug 23 00:27:01 1996 Jeffrey A Law (law@cygnus.com)
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
-start-sanitize-d10v
Thu Aug 15 13:14:43 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c: Add additional information to the opcode
table to help determinine which instructions can be done
in parallel.
-end-sanitize-d10v
Thu Aug 15 13:11:13 1996 Stan Shebs <shebs@andros.cygnus.com>
* mpw-make.sed: Update editing of include pathnames to be
* alpha-opc.c (EV4EXTHWINDEX): Field width should be 8 not 5.
-start-sanitize-d10v
Mon Aug 12 14:30:37 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Minor fixes to addi and bl.l.
* d10v-opc.c (d10v_opcodes): Correct 'mv' unit entry to EITHER.
-end-sanitize-d10v
Thu Aug 8 12:43:52 1996 Klaus Kaempf <kkaempf@progis.de>
* makefile.vms: Update for alpha-opc changes.
* i386-dis.c (print_insn_i386): Actually return the correct value.
(ONE, OP_ONE): #ifdef out; not used.
-start-sanitize-d10v
Fri Aug 2 17:47:03 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_opcodes): Added 2 accumulator sub instructions.
Changed subi operand type to treat 0 as 16.
-end-sanitize-d10v
Wed Jul 31 16:21:41 1996 Ian Lance Taylor <ian@cygnus.com>
* m68k-opc.c: Add cpushl for the mcf5200. From Ken Rose
* arm-dis.c: (print_insn_arm): Provide decoding of the new
formats %h and %s.
-start-sanitize-d10v
Fri Jul 26 11:45:04 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (d10v_operands): Added UNUM4S; a 4-bit accumulator shift.
(d10v_opcodes): Modified accumulator shift instructions to use UNUM4S.
-end-sanitize-d10v
Fri Jul 26 14:01:43 1996 Ian Lance Taylor <ian@cygnus.com>
* alpha-dis.c (print_insn_alpha_osf): Remove.
names based on info->flavour.
* disassemble.c: Always return print_insn_alpha for the alpha.
-start-sanitize-d10v
Thu Jul 25 15:24:17 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-dis.c (dis_long): Handle unknown opcodes.
* d10v-dis.c: Change all functions to use info->print_address_func.
-end-sanitize-d10v
Mon Jul 22 15:38:53 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Make opcode masks for the ColdFire
move ccr/sr insns more strict so that the disassembler only
selects them when the addressing mode is data register.
-start-sanitize-d10v
Mon Jul 22 11:25:24 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* d10v-opc.c (pre_defined_registers): Declare.
* d10v-dis.c (print_operand): Now uses pre_defined_registers
to pick a better name for the registers.
-end-sanitize-d10v
Mon Jul 22 13:47:23 1996 Ian Lance Taylor <ian@cygnus.com>
* sparc-opc.c: Fix opcode values for fpack16, and fpackfix. Fix
* configure: Rebuild.
* Makefile.in (install): Use @INSTALL_SHLIB@.
-start-sanitize-d10v
- Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+Wed Jul 17 14:39:05 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* configure: (bfd_d10v_arch) Add new case.
* configure.in: (bfd_d10v_arch) Add new case.
* d10v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d10v.
-end-sanitize-d10v
Wed Jul 17 10:12:05 1996 J.T. Conklin <jtc@rtl.cygnus.com>
* m68k-opc.c (m68k_opcodes): Fix bugs in coldfire insns relating
projects / deliverable / binutils-gdb.git / blobdiff