+2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
+
+2004-07-22 Nick Clifton <nickc@redhat.com>
+
+ PR/280
+ * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
+ insns - this is done by objdump itself.
+ * h8500-dis.c (print_insn_h8500): Likewise.
+
+2004-07-21 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
+ regardless of address size prefix in effect.
+ (ptr_reg): Size or address registers does not depend on rex64, but
+ on the presence of an address size override.
+ (OP_MMX): Use rex.x only for xmm registers.
+ (OP_EM): Use rex.z only for xmm registers.
+
+2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
+ move/branch operations to the bottom so that VR5400 multimedia
+ instructions take precedence in disassembly.
+
+2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
+
+ * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
+ ISA-specific "break" encoding.
+
+2004-07-13 Elvis Chiang <elvisfb@gmail.com>
+
+ * arm-opc.h: Fix typo in comment.
+
+2004-07-11 Andreas Schwab <schwab@suse.de>
+
+ * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
+
+2004-07-09 Andreas Schwab <schwab@suse.de>
+
+ * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
+
+2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
+
+ * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
+ (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
+ (crx-dis.lo): New target.
+ (crx-opc.lo): Likewise.
+ * Makefile.in: Regenerate.
+ * configure.in: Handle bfd_crx_arch.
+ * configure: Regenerate.
+ * crx-dis.c: New file.
+ * crx-opc.c: New file.
+ * disassemble.c (ARCH_crx): Define.
+ (disassembler): Handle ARCH_crx.
+
+2004-06-29 James E Wilson <wilson@specifixinc.com>
+
+ * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
+ * ia64-asmtab.c: Regnerate.
+
+2004-06-28 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
+ (extract_fxm): Don't test dialect.
+ (XFXFXM_MASK): Include the power4 bit.
+ (XFXM): Add p4 param.
+ (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
+
+2004-06-27 Alexandre Oliva <aoliva@redhat.com>
+
+ 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
+ * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
+
+2004-06-26 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (BH, XLBH_MASK): Define.
+ (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
+
+2004-06-24 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-dis.c (x_mode): Comment.
+ (two_source_ops): File scope.
+ (float_mem): Correct fisttpll and fistpll.
+ (float_mem_mode): New table.
+ (dofloat): Use it.
+ (OP_E): Correct intel mode PTR output.
+ (ptr_reg): Use open_char and close_char.
+ (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
+ operands. Set two_source_ops.
+
+2004-06-15 Alan Modra <amodra@bigpond.net.au>
+
+ * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
+ instead of _raw_size.
+
+2004-06-08 Jakub Jelinek <jakub@redhat.com>
+
+ * ia64-gen.c (in_iclass): Handle more postinc st
+ and ld variants.
+ * ia64-asmtab.c: Rebuilt.
+
+2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+ * s390-opc.txt: Correct architecture mask for some opcodes.
+ lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
+ in the esa mode as well.
+
+2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh-dis.c (target_arch): Make unsigned.
+ (print_insn_sh): Replace (most of) switch with a call to
+ sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
+ * sh-opc.h: Redefine architecture flags values.
+ Add sh3-nommu architecture.
+ Reorganise <arch>_up macros so they make more visual sense.
+ (SH_MERGE_ARCH_SET): Define new macro.
+ (SH_VALID_BASE_ARCH_SET): Likewise.
+ (SH_VALID_MMU_ARCH_SET): Likewise.
+ (SH_VALID_CO_ARCH_SET): Likewise.
+ (SH_VALID_ARCH_SET): Likewise.
+ (SH_MERGE_ARCH_SET_VALID): Likewise.
+ (SH_ARCH_SET_HAS_FPU): Likewise.
+ (SH_ARCH_SET_HAS_DSP): Likewise.
+ (SH_ARCH_UNKNOWN_ARCH): Likewise.
+ (sh_get_arch_from_bfd_mach): Add prototype.
+ (sh_get_arch_up_from_bfd_mach): Likewise.
+ (sh_get_bfd_mach_from_arch_set): Likewise.
+ (sh_merge_bfd_arc): Likewise.
+
+2004-05-24 Peter Barada <peter@the-baradas.com>
+
+ * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
+ into new match_insn_m68k function. Loop over canidate
+ matches and select first that completely matches.
+ * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
+ * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
+ to verify addressing for MAC/EMAC.
+ * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
+ reigster halves since 'fpu' and 'spl' look misleading.
+ * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
+ * m68k-opc.c: Rearragne mac/emac cases to use longest for
+ first, tighten up match masks.
+ * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
+ 'size' from special case code in print_insn_m68k to
+ determine decode size of insns.
+
+2004-05-19 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
+ well as when -mpower4.
+
+2004-05-13 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2004-05-05 Peter Barada <peter@the-baradas.com>
+
+ * m68k-dis.c(print_insn_m68k): Add new chips, use core
+ variants in arch_mask. Only set m68881/68851 for 68k chips.
+ * m68k-op.c: Switch from ColdFire chips to core variants.
+
+2004-05-05 Alan Modra <amodra@bigpond.net.au>
+
+ PR 147.
+ * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
+
+2004-04-29 Ben Elliston <bje@au.ibm.com>
+
+ * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
+ (powerpc_opcodes): Add "dbczl" instruction for PPC970.
+
+2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
+
+ * sh-dis.c (print_insn_sh): Print the value in constant pool
+ as a symbol if it looks like a symbol.
+
+2004-04-22 Peter Barada <peter@the-baradas.com>
+
+ * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
+ appropriate ColdFire architectures.
+ (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
+ mask addressing.
+ Add EMAC instructions, fix MAC instructions. Remove
+ macmw/macml/msacmw/msacml instructions since mask addressing now
+ supported.
+
+2004-04-20 Jakub Jelinek <jakub@redhat.com>
+
+ * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
+ (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
+ suffix. Use fmov*x macros, create all 3 fpsize variants in one
+ macro. Adjust all users.
+
+2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
+
+ * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
+ separately.
+
+2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
+
+ * m32r-asm.c: Regenerate.
+
+2004-03-29 Stan Shebs <shebs@apple.com>
+
+ * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
+ used.
+
+2004-03-19 Alan Modra <amodra@bigpond.net.au>
+
+ * aclocal.m4: Regenerate.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2004-03-16 Alan Modra <amodra@bigpond.net.au>
+
+ * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
+ PPC_OPERANDS_GPR_0.
+ * ppc-opc.c (RA0): Define.
+ (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
+ (RAOPT): Rename from RAO. Update all uses.
+ (powerpc_opcodes): Use RA0 as appropriate.
+
+2004-03-15 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
+
+2004-03-15 Alan Modra <amodra@bigpond.net.au>
+
+ * sparc-dis.c (print_insn_sparc): Update getword prototype.
+
+2004-03-12 Michal Ludvig <mludvig@suse.cz>
+
+ * i386-dis.c (GRPPLOCK): Delete.
+ (grps): Delete GRPPLOCK entry.
+
+2004-03-12 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
+ (M, Mp): Use OP_M.
+ (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
+ (GRPPADLCK): Define.
+ (dis386): Use NOP_Fixup on "nop".
+ (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
+ (twobyte_has_modrm): Set for 0xa7.
+ (padlock_table): Delete. Move to..
+ (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
+ and clflush.
+ (print_insn): Revert PADLOCK_SPECIAL code.
+ (OP_E): Delete sfence, lfence, mfence checks.
+
+2004-03-12 Jakub Jelinek <jakub@redhat.com>
+
+ * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
+ (INVLPG_Fixup): New function.
+ (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
+
+2004-03-12 Michal Ludvig <mludvig@suse.cz>
+
+ * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
+ (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
+ (padlock_table): New struct with PadLock instructions.
+ (print_insn): Handle PADLOCK_SPECIAL.
+
+2004-03-12 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
+ (OP_E): Twiddle clflush to sfence here.
+
+2004-03-08 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
+ nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
+ * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
+ accordingly.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * frv-asm.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * frv-desc.h: Regenerate.
+ * frv-dis.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * frv-opc.c: Regenerate.
+ * frv-opc.h: Regenerate.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * frv-desc.c, frv-opc.c: Regenerate.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
+
+2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
+ Also correct mistake in the comment.
+
+2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
+
+ * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
+ ensure that double registers have even numbers.
+ Add REG_N_B01 for nn01 (binary 01) nibble to ensure
+ that reserved instruction 0xfffd does not decode the same
+ as 0xfdfd (ftrv).
+ * sh-opc.h: Add REG_N_D nibble type and use it whereever
+ REG_N refers to a double register.
+ Add REG_N_B01 nibble type and use it instead of REG_NM
+ in ftrv.
+ Adjust the bit patterns in a few comments.
+
+2004-02-25 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
+
+2004-02-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
+
+2004-02-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
+
+2004-02-20 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
+ mtivor32, mtivor33, mtivor34.
+
+2004-02-19 Aldy Hernandez <aldyh@redhat.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add mfmcar.
+
+2004-02-10 Petko Manolov <petkan@nucleusys.com>
+
+ * arm-opc.h Maverick accumulator register opcode fixes.
+
+2004-02-13 Ben Elliston <bje@wasabisystems.com>
+
+ * m32r-dis.c: Regenerate.
+
+2004-01-27 Michael Snyder <msnyder@redhat.com>
+
+ * sh-opc.h (sh_table): "fsrra", not "fssra".
+
+2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
+
+ * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
+ contraints.
+
+2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
+
+ * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
+
+2004-01-19 Alan Modra <amodra@bigpond.net.au>
+
+ * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
+ 1. Don't print scale factor on AT&T mode when index missing.
+
2004-01-16 Alexandre Oliva <aoliva@redhat.com>
* m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
projects / deliverable / binutils-gdb.git / blobdiff