x86: Replace IgnoreSize/DefaultSize with MnemonicSize

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 73091b9e61d16bef786188b8c2238cbc5bfaa591..6508515fa875baa45a1bf20b35c4a9210653a9a2 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,48 @@
+2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
+       with MnemonicSize.
+       * i386-opc.h (IGNORESIZE): New.
+       (DEFAULTSIZE): Likewise.
+       (IgnoreSize): Removed.
+       (DefaultSize): Likewise.
+       (MnemonicSize): New.
+       (i386_opcode_modifier): Replace ignoresize/defaultsize with
+       mnemonicsize.
+       * i386-opc.tbl (IgnoreSize): New.
+       (DefaultSize): Likewise.
+       * i386-tbl.h: Regenerated.
+
+2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
+
+       PR 25627
+       * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
+       instructions.
+
+2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/25622
+       * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
+       vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
+       * i386-tbl.h: Regenerated.
+
+2020-02-26  Alan Modra  <amodra@gmail.com>
+
+       * aarch64-asm.c: Indent labels correctly.
+       * aarch64-dis.c: Likewise.
+       * aarch64-gen.c: Likewise.
+       * aarch64-opc.c: Likewise.
+       * alpha-dis.c: Likewise.
+       * i386-dis.c: Likewise.
+       * nds32-asm.c: Likewise.
+       * nfp-dis.c: Likewise.
+       * visium-dis.c: Likewise.
+
+2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
+
+       * arc-regs.h (int_vector_base): Make it available for all ARC
+       CPUs.
+
 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 
        * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is