+start-sanitize-am33
+Thu Jul 16 18:04:46 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and
+ "mulu".
+
+end-sanitize-am33
+start-sanitize-r5900
+Mon Jul 13 18:14:24 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (pref): Enabled for the r5900.
+
+end-sanitize-r5900
+Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c (ckprefix): Handle fwait specially only when it isn't
+ the first prefix.
+ (dofloat): Correct test for fnstsw. Print `fnstsw %ax' rather
+ than `fnstsw %eax'.
+ (OP_J): Remove unnecessary subtraction when 16-bit displacement
+ will be masked later.
+
+start-sanitize-am33
+Fri Jul 10 23:09:56 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c (mn10300_opcodes): Fix destination operand for 3 operand
+ instructions.
+
+Wed Jul 8 11:32:44 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-dis.c (disassemble): When printing RREGs and XRREGs, map
+ from raw register #s to symbolic names to make debugging easier.
+
+end-sanitize-am33
+Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * m32r-opc.h (CGEN_MIN_INSN_SIZE): New #define.
+
+Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate.
+start-sanitize-cygnus
+ * Makefile.am (CGENDIR): Set via configure.
+ (CGEN): New variable.
+ (CGENFILES): object.scm renamed to cos.scm.
+ (run-cgen): Renamed from cgen. stamp file renamed to stamp-$prefix.
+ (stamp-m32r): Pass prefix to run-cgen.
+ * Makefile.in: Regenerate.
+ * cgen-asm.in: @arch@-opc.h renamed to @prefix@-opc.h.
+ * cgen-dis.in: Ditto.
+ * cgen-opc.in: Ditto.
+ * cgen.sh: New args cgen,prefix. Delete args scheme,schemeflags.
+ * configure.in: AC_SUBST cgen,cgendir. No longer look for guile.
+ * configure: Regenerate.
+end-sanitize-cygnus
+
+start-sanitize-am33
+Tue Jun 30 09:59:37 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Reorder "movbu" and "movhu" instructions too.
+
+Mon Jun 29 14:54:32 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Reorder more instructions so that we do not
+ accidentally match a mn10300 instruction when we really
+ wanted an am33 instruction.
+
+end-sanitize-am33
+Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-dis.c: Only recognize instructions from the currently
+ selected machine.
+ * m10300-opc.c: Add field indicating the particular variant of
+ the mn10300 each instruction is available on.
+
+Fri Jun 26 12:04:21 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in: For bfd_vax_arch, build vax-dis.lo.
+ * Makefile.am: Rebuild dependencies.
+ (CFILES): Add vax-dis.c.
+ (ALL_MACHINES): Add vax-dis.lo.
+ * aclocal.m4: Rebuild with current libtool.
+ * configure, Makefile.in: Rebuild.
+
+Fri Jun 26 12:03:20 1998 Klaus Kaempf <kkaempf@progis.de>
+
+ * vax-dis.c: New file, from work by Pauline Middelink
+ <middelin@polyware.iaf.nl>.
+ * disassemble.c (ARCH_vax): Define if ARCH_all.
+ (disassembler): Add case for ARCH_vax.
+ * makefile.vms: Support compilation on vms/vax.
+
+start-sanitize-sky
+Wed Jun 24 17:14:01 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * dvp-opc.c (DVP_OPERAND_RELOC_11_S4): Temporarily back out
+ the DVP_OPERAND_RELOC_11_S4 relocation.
+
+end-sanitize-sky
+start-sanitize-am33
+Wed Jun 24 09:53:06 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-dis.c (print_insn_mn10300): 0xf7 opcode prefix specifies
+ 4 byte instructions.
+ (disassemble): Correctly handle FMT_D10 instructions.
+
+ * m10300-opc.c (mn10300_opcodes): Fix typo in IMM24 versions of the
+ am33 shift instructions.
+
+ * m10300-dis.c (print_insn_mn10300): 0xf9 opcode prefix specifies
+ 3 byte instructions.
+ (disassemble): Handle new instruction formats FMT_D6, FMT_D7, FMT_D8
+ FMT_D9 and FMT_D10. Handle various new opcode flags for the am33.
+
+ * m10300-opc.c (IMM32_HIGH8_MEM): New operand type.
+ (mn10300_opcodes): Reorder so as to try and select opcodes from
+ the core chip when multiple alternatives exist. Change several
+ am33 instructions to use IMM32_HIGH8_MEM. Fix typos in "mac" and
+ "macbu" instructions. Fix typos in a couple DSP instructions too.
+
+end-sanitize-am33
+Tue Jun 23 19:42:18 1998 Mark Alexander <marka@cygnus.com>
+
+ * m10200-dis.c (print_insn_mn10200): Fix various non-portabilities
+ related to sign extension and the size of ints.
+
+Tue Jun 23 10:59:26 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Support one operand "asr", "lsr" and "asl"
+ instructions. Support (sp) addressing mode by expanding it into
+ (0,sp).
+
+start-sanitize-sky
+Mon Jun 22 15:48:29 1998 Ian Carmichael <iancarm@cygnus.com>
+
+ * dvp-opc.c (LIMM11, LUIMM15): New symbol types
+ DVP_OPERAND_RELOC_U15_S3 and DVP_OPERAND_RELOC_11_S4 to allow labels to
+ be used as immediate values.
+
+end-sanitize-sky
+start-sanitize-am33
+Mon Jun 22 13:36:27 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Support 4 byte DSP instructions.
+
+end-sanitize-am33
+Sat Jun 20 14:46:20 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips-dis.c (_print_insn_mips): Fix argument interchange typo.
+
+start-sanitize-am33
+Fri Jun 19 16:47:06 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Support 6 and 7 byte am33 instructions.
+
+end-sanitize-am33
+Fri Jun 19 09:16:42 1998 Mark Alexander <marka@cygnus.com>
+
+ * m10200-dis.c (print_insn_mn10200): Recognize 'break' pseudo-op.
+
+start-sanitize-am33
+Fri Jun 19 09:42:51 1998 Jeffrey A Law (law@cygnus.com)
+
+ * m10300-opc.c: Support for 3 byte and 4 byte extended instructions
+ found on the mn10300.
+
+end-sanitize-am33
+1998-06-18 Ulrich Drepper <drepper@cygnus.com>
+
+ * i386-dis.c: Add support for fxsave, fxrstor, sysenter and
+ sysexit.
+
+Thu Jun 18 10:22:24 1998 John Metzler <jmetzler@cygnus.com>
+
+ * mips-dis.c (print_insn_little_mips): Previously, instruction
+ printing references the symbol table to determine whether the
+ instruction resides in a block regular instructions or mips16
+ instructions. However, when the disassembler gets used in other
+ environments where the symbol table is not present, we no longer
+ rely in the symbol table, rather, use the low bit of the
+ instructions address to guess. There should be no change for usage
+ of the disassembler in host based programse, gdb ,objdump.
+ (print_insn_big_mips): ditto.
+ (print_insn_mips): ditto
+
+Wed Jun 17 21:19:01 1998 Mark Alexander <marka@cygnus.com>
+
+ * m10200-dis.c (print_insn_mn10200): Don't bomb on unknown opcodes.
+
+Wed Jun 17 17:49:23 1998 Jeffrey A Law (law@cygnus.com)
+
+start-sanitize-am33
+ * m10300-opc.c (USP, SSP, MSP, PC, IMM4, EPSW, RN0, RM1): New
+ operands for the am33.
+ (mn10300_opcodes): Add new instructions from the am33.
+end-sanitize-am33
+ * m10300-opc.c (mn10300_opcodes): Change opcode for "syscall".
+
+Tue Jun 16 13:10:51 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c (index16): Add '%' to register names. Use ','
+ instead of '+'.
+
+Sat Jun 13 11:33:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c: Don't print opcode suffix when we can figure out the
+ size (and gas can!) by register operands, or from the default
+ size.
+ (putop): Handle 'A', 'B', 'L', 'P', 'Q', 'R' macros. Rename 'C'
+ macro to 'E'.
+ (dis386, dis386_twobyte, grps): Use new suffix macros.
+ (dis386): Correct imul Ib to imul sIb. Change jnl to jge to be
+ consistent. Add suffix for call, jmp, lcall, ljmp, iret. Reverse
+ order of cmps operands to agree with Intel docs. Correct operand
+ of aad and aam (Ib -> sIb). Change ud2b from 0fb8 to 0fb9 to
+ agree with Intel docs.
+ (print_insn_x86): Print orphan fwait before other prefixes.
+ Return correct byte count for orphan fwait with prefixes. Don't
+ print `bound' operands in reverse order.
+ (ckprefix): Stop accumulating prefixes if we get fwait.
+ (OP_DIR): Print `$' before Ap operands of ljmp, lcall.
+
+Fri Jun 12 13:40:38 1998 Tom Tromey <tromey@cygnus.com>
+
+ * po/Make-in (all-yes): If maintainer mode, depend on .pot file.
+ ($(PACKAGE).pot): Unconditionally depend on POTFILES.
+
+Fri Jun 12 11:04:06 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ Fix problems when bfd_vma is wider than long.
+ * i386-dis.c: Make op_address and start_pc unsigned.
+ (set_op): Make parameter unsigned.
+ (print_insn_x86): Cast to bfd_vma when passing a value to
+ print_address_func.
+ * ns32k-dis.c (CORE_ADDR): Don't define.
+ (print_insn_ns32k): Change type of addr to bfd_vma. Use
+ bfd_scan_vma to read back address.
+ (print_insn_arg): Change type of addr to bfd_vma. Use sprintf_vma
+ to format it.
+ * m68k-dis.c (COERCE32): Cast to bfd_signed_vma to avoid overflow.
+ (NEXTULONG): New definition.
+ (print_insn_m68k): Avoid overflow when computing third argument of
+ print_insn_arg.
+ (print_insn_arg): Use NEXTULONG to fetch 32 bit address values.
+ Use disp instead of val to store offset values.
+ (print_indexed): Use base_disp instead of word to store base
+ displacement, to avoid overflow.
+ * m10300-dis.c (disassemble): Cast value to long when computing
+ pc-relative address, to get correct sign extension.
+
+Wed Jun 10 15:58:37 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * m32r-opc.c: Regenerate.
+
+Tue Jun 9 14:27:57 1998 Nick Clifton <nickc@cygnus.com>
+
+ * arm-opc.h (thumb_opcodes): Display 'add rx, rY, #0' insns as
+ 'mov rX, rY'. Patch courtesy of Tony Thompson <Tony.Thompson@arm.com>
+
+Mon Jun 8 18:17:21 1998 Nick Clifton <nickc@cygnus.com>
+
+ * d30v-opc.c: Remove FALG_MUL32 attribyte from MULX2H insn.
+
+Fri Jun 5 23:47:55 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
+
+ * i386-dis.c: Combine aflag and dflag into sizeflag. Change OP_*
+ functions to void.
+ (OP_DSreg): Rename from OP_DSSI.
+ (OP_ESreg): Rename from OP_ESDI.
+ (Xb, Xv, Yb, Yv): Use index reg code, not b_mode or v_mode.
+ (DSBX): Define.
+ (append_seg): Rename from append_prefix.
+ (ptr_reg): New function.
+ (dis386): Add S suffix to pushf, popf, ret, lret, enter, leave.
+ Add DSBX for xlat.
+ (PREFIX_ADDR): Rename from PREFIX_ADR.
+ (float_reg): Add non-broken opcodes for people who don't want
+ UNIXWARE_COMPAT.
+
+Fri Jun 5 19:15:04 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
+
+ * m68k-opc.c (tstb, tstw, tstl): Don't allow pcrel on
+ 68000/68008/68010.
+
+Wed Jun 3 18:56:22 1998 H.J. Lu <hjl@gnu.org>
+
+ * i386-dis.c (dis386): Change 0x60 to "pushaS", 0x61 to "popaS".
+
+Tue Jun 2 15:06:46 1998 Geoff Keating <geoffk@ozemail.com.au>
+
+ * ppc-opc.c (powerpc_macros): Support shifts and rotates of size
+ 0; produce error message for shifts of size 32 (or 64 for 64-bit
+ shifts), because the hardware doesn't support them.
+
+start-sanitize-r5900
+Mon Jun 1 10:27:26 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (c.lt.s): Remove r5900 specific variant.
+ (c.le.s): Likewise.
+
+ * vu0.h (sqc2): Fix opcode.
+
+ * mips-opc.c (rsqrt.s): Update based on r5900 ISA manual version 2.1
+ (sqrt.s): Likewise.
+
+end-sanitize-r5900
+start-sanitize-vr5400
+Thu May 28 08:46:09 1998 Catherine Moore <clm@cygnus.com>
+
+ * mips-opc.c (macc, maccu, macchi, macchiu, msac, msacu, msachi, msachiu):
+ Change pinfo to use WR_HILO.
+
+end-sanitize-vr5400
+start-sanitize-d30v
+Wed May 27 15:29:13 1998 Nick Clifton <nickc@cygnus.com>
+
+ * d30v-opc.c: Add new operand: Ra3. Change SHORT_B3, SHORT_B3b,
+ LONG_2, LONG_2b formats to use this new operand.
+
+end-sanitize-d30v
+Tue May 26 20:47:48 1998 Stan Cox <scox@cygnus.com>
+
+ * sparc-dis.c (compute_arch_mask): Added bfd_mach_sparc_sparclite_le.
+
+Tue May 26 20:45:33 1998 Mark Alexander <marka@cygnus.com>
+
+ * sparc-dis.c (print_insn_sparc): big endian instruction / little
+ endian data support.
+
+start-sanitize-d30v
+Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com>
+
+ * d30v-opc.c (d30v_format_table): Change definition of SHORT_B3
+ and SHORT_B3b formats to use Rb instead of Ra.
+
+ Add FLAG_MUL16 to MUL2XH opcode.
+
+ Add FLAG_ADDSUBppp to SRC and SATHp opcodes to implement extension
+ to existing 1.1.1 parallelisation prohibition procedure.
+
+end-sanitize-d30v
+Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * cgen-asm.in (insert_normal): Handle empty fields and 64 bit hosts.
+ * cgen-dis.in (extract_normal): Likewise.
+ * m32r-asm.c,m32r-dis.c: Regenerate.
+
+start-sanitize-sky
+Fri May 22 11:44:10 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * dvp-opc.c (parse_dotdest): Missing dest -> xyzw.
+
+end-sanitize-sky
+start-sanitize-r5900
+Wed May 20 00:22:27 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-opc.c (multu1): Add two operand variant for the r5900.
+
+end-sanitize-r5900
+Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Handle type ']' correctly
+ with a shift count of 0.
+
+start-sanitize-r5900
+Mon May 18 14:27:06 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips-opc.c (mult1): Add two-operand variety of mult1 for R5900.
+
+Mon May 18 11:44:00 1998 Jeffrey A Law (law@cygnus.com)
+
+ * mips-dis.c (print_insn_arg): Handle ';' opcode completer.
+ (_print_insn_mips): Likewise.
+ * vu0.h (vopmula, vopmsub): Correctly handle opcode/operand
+ completers.
+
+end-sanitize-r5900
+Fri May 15 14:58:31 1998 Doug Evans <devans@seba.cygnus.com>
+
+ * cgen-opc.c (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup.
+ (cgen_hw_lookup_by_num): New function.
+
+start-sanitize-m32rx
+ * m32r-opc.c, m32r-opc.h: Regenerate, delete h-abort.
+
+end-sanitize-m32rx
+Wed May 13 17:03:59 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * m32r-asm.c: Regenerate (handle uppercase HIGH/SHIGH/LOW/SDA).
+
+Wed May 13 14:34:31 1998 Mark Alexander <marka@cygnus.com>
+
+ * sparc-dis.c (print_insn_sparc): Always fetch instructions
+ as big-endian on SPARClite.
+
+start-sanitize-m32rx
+Tue May 12 13:39:51 1998 Nick Clifton <nickc@cygnus.com>
+
+ * m32r-opc.c: Regenerated - SPECIAL attribute added to some
+ insns.
+ * m32r-opc.h: Regenerated - SPECIAL attribute added to some
+ insns.
+
+end-sanitize-m32rx
+start-sanitize-d30v
+Tue May 12 11:46:31 1998 Richard Henderson <rth@cygnus.com>
+
+ * d30v-opc.c (pre_defined_register): Remove alias for r0.
+
+end-sanitize-d30v
+start-sanitize-r5900
+Mon May 11 13:12:15 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips-opc.c (break): Added 20-bit single-operand break
+ instruction for R5900 only.
+
+end-sanitize-r5900
+Sun May 10 22:37:22 1998 Jeffrey A Law (law@cygnus.com)
+
+ * po/Make-in (install-info): New target.
+
+Thu May 7 17:15:59 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure.in (WIN32LIBADD): Add -lintl on cygwin32.
+ * configure: Rebuild.
+
+Thu May 7 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips-opc.c (teq,tge,tgeu,tlt,tltu,tne): Added three-operand
+ variety of ISA2 instructions to set bottom ten bits of trap code.
+
+Thu May 7 11:54:25 1998 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.am (config.status): Add explicit target so that
+ config.status depends upon bfd/configure.in.
+ * Makefile.in: Rebuild.
+
+Thu May 7 09:33:02 1998 Frank Ch. Eigler <fche@cygnus.com>
+
+ * mips-opc.c (break, sdbbp): Added two-operand variety of ISA1
+ instructions to set bottom ten bits of break code.
+ * mips-dis.c (print_insn_arg): Implement 'q' operand format used
+ for above optional argument.
+
start-sanitize-cygnus
Wed May 6 14:47:17 1998 Doug Evans <devans@seba.cygnus.com>
* dis-buf.c: Internationalised.
start-sanitize-sky
* dvp-dis.c: Internationalised.
- * dvp-opc.c: Internationalised.
* dvp-opc.c: Internationalised.
end-sanitize-sky
* h8300-dis.c: Internationalised.
Mon Apr 13 16:59:39 1998 Nick Clifton <nickc@cygnus.com>
* arm-dis.c (print_insn_arm): Add "_all" extension to 'C'
- operator.
+ operator.
Mon Apr 13 16:50:27 1998 Ian Lance Taylor <ian@cygnus.com>
* ns32k-dis.c (bit_extract_simple): New function to extract bits
from an arbitrary valid buffer instead of fetching them on demand
- using fetch_data().
+ using fetch_data().
(invalid_float): use bit_extract_simple() instead of bit_extract().
start-sanitize-m32rx
Wed Apr 1 14:57:54 1998 Nick Clifton <nickc@cygnus.com>
- * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
- * m32r-opc.h: Add extra control registers.
+ * m32r-opc.c: Fix SATB bit pattern. Add extra control registers.
+ * m32r-opc.h: Add extra control registers.
end-sanitize-m32rx
Tue Mar 31 11:09:08 1998 Ian Lance Taylor <ian@cygnus.com>
start-sanitize-r5900
Fri Mar 20 09:01:31 1998 Jeffrey A Law (law@cygnus.com)
- * mips-dis.c: Change '%' to '#' to avoid conflict with vr5400
- support.
+ * mips-dis.c: Change '%' to '#' in r5900 support.
* vu0.h: Likewise.
end-sanitize-r5900
These patches are courtesy of Jonathan Walton and Tony Thompson
(athompso@cambridge.arm.com).
-
+
* arm-dis.c (print_insn_thumb): Ignore bottom two bits of PC
relative addresses.
Fri Feb 13 09:50:32 1998 Nick Clifton <nickc@cygnus.com>
- * m32r-opc.c: Regenerate.
- * m32r-opc.h: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
Thu Feb 12 11:01:40 1998 Doug Evans <devans@canuck.cygnus.com>
* arm-dis.c (print_insn_little_arm): Prevent examination of stored
symbol if none is present.
(print_insn_big_arm): Prevent examination of stored symbol if
- none is present.
+ none is present.
Thu Oct 23 21:13:37 1997 Fred Fish <fnf@cygnus.com>
-
+
* d10v-opc.c (d10v_opcodes): Correct entry for RTE.
-
+
Mon Dec 8 11:21:07 1997 Nick Clifton <nickc@cygnus.com>
* disassemble.c: Remove disasm_symaddr() function.
start-sanitize-tx49
Wed Oct 29 15:10:56 1997 Gavin Koch <gavin@cygnus.com>
- * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
+ * mips-opc.c (deret,dmult,dmultu,madd,maddu,pref,sdbbp):
Add tx49 insns and configury.
end-sanitize-tx49
Tue Sep 16 15:18:20 1997 Nick Clifton <nickc@cygnus.com>
- * v850-opc.c (v850_opcodes): Further rearrangements.
+ * v850-opc.c (v850_opcodes): Further rearrangements.
start-sanitize-d30v
Tue Sep 16 16:12:11 1997 Ken Raeburn <raeburn@cygnus.com>
and cmp instructions.
* d30v-opc.c: Correct entries for repeat*, and sat*.
- Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
+ Make IMM5 unsigned. Create IMM6U and IMM12S3U operand
types. Correct several formats.
* d30v-opc.c: (pre_defined_registers): Add dpsw and dpc.
New form: SHORT_A2; a SHORT_A form that needs an even
register as the first operand.
- * d30v-dis.c (print_insn_d30v): Fix problem where the last
+ * d30v-dis.c (print_insn_d30v): Fix problem where the last
instruction was not being disassembled if there were an odd
number of instructions.
start-sanitize-v850e
* v850-dis.c (disassemble): Add support for v850EA instructions.
-
+
* v850-opc.c (insert_i5div, extract_i5div): New Functions.
(v850_opcodes): Add v850EA instructions.
* v850-dis.c (disassemble): Add support for v850E instructions.
-
+
* v850-opc.c (insert_d5_4, extract_d5_4, insert_d16_16,
extract_d16_16, insert_i9, extract_i9, insert_u9, extract_u9,
insert_spe, extract_spe): New Functions.
(v850_opcodes): Add v850E instructions.
end-sanitize-v850e
-
+
* v850-opc.c: Reorganised and re-layed out to improve readability
and portability.
negating it.
(UNUSED): remove one level of parens, so MSVC doesn't choke on
nesting depth when all the macros are expanded.
-
+
Tue Jun 17 17:02:17 1997 Ian Lance Taylor <ian@cygnus.com>
* sparc-opc.c: The fcmp v9a instructions take an integer register
Tue May 20 11:26:27 1997 Gavin Koch <gavin@cygnus.com>
- * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
+ * mips-opc.c (mips_builtin_opcodes): Moved INSN_ISA field into new
field membership.
* mips16-opc.c (mip16_opcodes): same.
* m68k-opc.c (m68k_opcodes): Provide coldfire division module
instructions.
-
+
end-sanitize-coldfire
Tue Mar 18 14:17:03 1997 Jeffrey A Law (law@cygnus.com)
* m68k-opc.c (m68k_opcodes): Provide correct entries for mulsl and
mulul insns on the coldfire.
-
+
Sat Mar 15 17:13:05 1997 Ian Lance Taylor <ian@cygnus.com>
* arm-dis.c (print_insn_arm): Don't print instruction bytes.
* m68k-opc.c (m68k_opcodes): Added entries for the tst insns on
the mc68000.
-
+
Thu Feb 27 14:04:32 1997 Philippe De Muyter <phdm@info.ucl.ac.be>
* m68k-opc.c (m68k_opcodes): Added swbegl pseudo-instruction.
Mon Feb 24 15:19:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
- * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
+ * d10v-dis.c, d10v-opc.c: Change pre_defined_registers to
d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt.
start-sanitize-tic80
Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
* mips-opc.c: Add macros for cop0, cop1 cop2 and cop3.
- Change mips_opcodes from const array to a pointer,
+ Change mips_opcodes from const array to a pointer,
and change bfd_mips_num_opcodes from const int to int,
- so that we can increase the size of the mips opcodes table
+ so that we can increase the size of the mips opcodes table
dynamically.
start-sanitize-tic80
* d30v-opc.c: Removed references to FLAG_X.
-end-sanitize-d30v
+end-sanitize-d30v
Wed Feb 19 14:51:20 1997 Ian Lance Taylor <ian@cygnus.com>
* Makefile.in: Add dependencies on ../bfd/bfd.h as required.
* d30v-opc.c: New file.
* disassemble.c (disassembler) Add entry for d30v.
-end-sanitize-d30v
+end-sanitize-d30v
start-sanitize-tic80
Tue Feb 18 16:32:08 1997 Fred Fish <fnf@cygnus.com>
- * tic80-opc.c (tic80_predefined_symbols): Add symbolic
+ * tic80-opc.c (tic80_predefined_symbols): Add symbolic
representations for the floating point BITNUM values.
Fri Feb 14 12:14:05 1997 Fred Fish <fnf@cygnus.com>
start-sanitize-r5900
Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
-
+
* mips-opc.c: add r5900.
-
+
end-sanitize-r5900
start-sanitize-tic80
Mon Feb 10 10:12:41 1997 Fred Fish <fnf@cygnus.com>
* m68k-opc.c (m68k_opcodes): Changed operand specifier for the
coldfire moveb instruction to not allow an address register as
destination. Although the documentation does not indicate that
- this is invalid, experiments uncovered unexpected behavior.
+ this is invalid, experiments uncovered unexpected behavior.
Added a comment explaining the situation. Thanks to Andreas
Schwab for pointing this out to me.
entries are presorted so that entries with the same mnemonic are
adjacent to each other in the table. Sort the entries for each
instruction so that this is true.
-
+
end-sanitize-tic80
Mon Jan 20 12:48:57 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
"vsub", "vst", "xnor", and "xor" instructions.
(V_a1): Renamed from V_a, msb of accumulator reg number.
(V_a0): Add macro, lsb of accumulator reg number.
-
+
Fri Jan 17 18:24:31 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Broke excessively long
math instruction packed into a single opcode.
* tic80-opc.c (tic80_opcodes): Expand comment for vld opcode
to explain why it comes after the other vector opcodes.
-
+
end-sanitize-tic80
Fri Jan 17 16:19:15 1997 J.T. Conklin <jtc@beauty.cygnus.com>
- * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
+ * m68k-opc.c (m68k_opcodes): add b, w, or l specifier to coldfire
move insns to handle immediate operands.
-
+
Thu Jan 17 16:19:00 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (m68k_opcodes): Delete duplicate entry for "cmpil".
Remove some opcodes that are possible, but illegal, such
as long immediate instructions with doubles for immediate
values. Add "vadd" and "vld" instructions.
-
+
Wed Jan 15 18:59:51 1997 Fred Fish <fnf@cygnus.com>
* tic80-opc.c (tic80_operands): Reorder some table entries to make
followed by a tab. Use renamed TIC80_OPERAND_PCREL flag bit rather
than old TIC80_OPERAND_RELATIVE. Add support for new
TIC80_OPERAND_BASEREL flag bit.
-
+
Mon Jan 13 15:58:56 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Print floating point operands
(P2): Macro for the 'P2' field.
(P1): Macro for the 'P1' field.
(tic80_opcodes): Add entries for "exts", "extu", "fadd",
- "fcmp", and "fdiv".
-
+ "fcmp", and "fdiv".
+
end-sanitize-tic80
Mon Jan 6 15:06:55 1997 Jeffrey A Law (law@cygnus.com)
(print_insn_tic80): If R_SCALED then print ":s" modifier for operand.
* tic80-opc.c (REG0, REG22, REG27, SSOFF, LSOFF): Names
changed to REG_0, REG_22, REG_DEST, OFF_SS, OFF_SL respectively.
- (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
+ (SICR, LICR, REGM_SI, REGM_LI): Names changed to CR_SI, CR_LI,
REG_BASE_M_SI, REG_BASE_M_LI respectively.
(REG_SCALED, LSI_SCALED): New operand types.
(E): New macro for 'E' bit at bit 27.
(tic80_opcodes): Add and test dld, dld.u, dst, estop, and etrap
opcodes, including the various size flavors (b,h,w,d) for
the direct load and store instructions.
-
+
Sun Jan 5 12:18:14 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (M_SI, M_LI): Add macros to test for ":m" modifier bit
(MASK_LI_M, MASK_SI_M, MASK_REG_M): Remove and replace in opcode
masks with "MASK_* & ~M_*" to get the M bit reset.
(tic80_opcodes): Add bsr, bsr.a, cmnd, cmp, dcachec, and dcachef.
-
+
Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com>
* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
start-sanitize-tic80
(tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
end-sanitize-tic80
-
+
Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com>
* mips16-opc.c: Add "abs".
* configure: Regenerate with autoconf.
* tic80-dis.c: Add file.
* tic80-opc.c: Add file.
-
+
end-sanitize-tic80
Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
* m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
register operands for immediate arithmetic, not, neg, negx, and
set according to condition instructions.
-
+
* m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
specifier of the effective-address operand in immediate forms of
arithmetic instructions. The specifier for the immediate operand
* mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
opcode.
- * mn10300-dis.c (disassemble): Use '$' instead of '%' for
+ * mn10300-dis.c (disassemble): Use '$' instead of '%' for
register prefix.
* mn10300-dis.c (disassemble): Prefix registers with '%'.
* mn10300-opc.c (mn10300_operands): Add "REGS" for a register
list.
(mn10300_opcodes): Use REGS for register list in "movm" instructions.
-
+
Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
* d10v-opc.c (d10v_opcodes): Add3 sets the carry.
* mn10300-opc.c (mn10300_operands): Hijack "bits" field
in MN10300_OPERAND_SPLIT operands for how many bits
appear in the basic insn word. Add IMM32_HIGH24,
- IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
+ IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
(mn10300_opcodes): Use new operands as needed.
* mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
standard disassembly.
* alpha-opc.c (alpha_operands): Rearrange flags slot.
- (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
+ (alpha_opcodes): Add new BWX, CIX, and MAX instructions.
Recategorize PALcode instructions.
Wed Oct 30 16:46:58 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_opcodes): Add "extended" instructions,
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
-
+
Tue Oct 8 11:55:35 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Remove "REGS" operand.
Update many operand fields to deal with signed vs unsigned
issues. Fix one or two typos in the "mov" instruction
opcode, mask and/or operand fields.
-
+
Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de>
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
* configure: (bfd_v850v_arch) Add new case.
* configure.in: (bfd_v850_arch) Add new case.
* v850-opc.c: New file.
-
+
Mon Aug 19 15:21:38 1996 Doug Evans <dje@canuck.cygnus.com>
* sparc-dis.c (print_insn_sparc): Handle little endian sparcs.
* sh-opc.h (sh_arg_type): Add F_FR0.
(sh_table, case fmac): Add F_FR0 as first argument.
-
+
Wed Sep 6 15:08:09 1995 Jim Wilson <wilson@chestnut.cygnus.com>
* sh-opc.h (sh_opcode_info): Increase arg array size to 4.
* sh-opc.h: Added bsrf and braf.
-Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
+Wed May 10 14:28:16 1995 Richard Earnshaw (rearnsha@armltd.co.uk)
* arm-opc.h (arm_opcodes): Add 64-bit multiply patterns. Delete
bogus [ls]fm{ea,fd} patterns.
* mpw-config.in (target_arch): Compute from canonical target.
(m68k, mips, powerpc, sparc): Add architectures.
* mpw-make.in (disassemble.c.o): Add.
- (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
+ (ALL_CFLAGS): Remove special flags (-mc68020 -mc68881 -model far).
* mpw-config.in (BFD_MACHINES): Set to a default value.
* mpw-make.in (BFD_MACHINES): Remove wired-in value.
Mon Jan 17 20:05:49 1994 Jeffrey A. Law (law@snake.cs.utah.edu)
* hppa-dis.c (print_insn_hppa): Handle 'N' in assembler template.
- No space before 'u', 'f', or 'N'.
+ No space before 'u', 'f', or 'N'.
Sun Jan 16 14:20:16 1994 Jim Kingdon (kingdon@deneb.cygnus.com)
Sun Nov 7 23:52:34 1993 Peter Schauer (pes@regent.e-technik.tu-muenchen.de)
* alpha-opc.h, alpha-dis.c (print_insn_alpha): Add
- FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
+ FLOAT_MEMORY_FORMAT_CODE, FLOAT_BRANCH_FORMAT_CODE, correct
FLOAT_FORMAT_CODE to put out floating point register names.
Mon Nov 1 18:17:51 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com)
defined, since gdb has been fixed.
Changes from Jeff Law, law@cs.utah.edu:
- * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
+ * hppa-dis.c (print_insn_hppa): Last argument to fput_reg,
fput_reg_r, fput_creg, fput_const, and fputs_filtered should
be a *disassemble_info, not a *FILE.
* hppa-dis.c: Support 'd', '!', and 'a'.
projects / deliverable / binutils-gdb.git / blobdiff