+Fri Jan 3 12:13:52 1997 Ian Lance Taylor <ian@cygnus.com>
+
+ * m68k-opc.c: Add #B case for moveq.
+
+Thu Jan 2 12:14:29 1997 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disassemble): Make sure all variables are initialized
+ before they are used.
+
+start-sanitize-v850
+Tue Dec 31 12:20:38 1996 Jeffrey A Law (law@cygnus.com)
+
+ * v850-opc.c (v850_opcodes): Put curly-braces around operands
+ for "breakpoint" instruction.
+
+end-sanitize-v850
+Tue Dec 31 15:38:13 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * Makefile.in (ALL_CFLAGS): Add -D_GNU_SOURCE.
+ (dep): Use ALL_CFLAGS rather than CFLAGS.
+
+start-sanitize-v850
+Tue Dec 31 15:09:16 1996 Michael Meissner <meissner@tiktok.cygnus.com>
+
+ * v850-opc.c (D8_{6,7}): Set V850_OPERAND_ADJUST_SHORT_MEMORY
+ flag.
+
+end-sanitize-v850
+Mon Dec 30 17:02:11 1996 Fred Fish <fnf@cygnus.com>
+
+ * Makefile.in (m68k-opc.o, alpha-opc.o): Remove dis-asm.h dependency.
+start-sanitize-tic80
+ (tic80-dis.o, tic80-opc.o): Add rules per comment in Makefile.in.
+end-sanitize-tic80
+
+Mon Dec 30 11:38:01 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Add "abs".
+
+start-sanitize-tic80
+Sun Dec 29 10:58:22 1996 Fred Fish <fnf@cygnus.com>
+
+ * Makefile.in (ALL_MACHINES): Add tic80-dis.o and tic80-opc.o.
+ * disassemble.c (ARCH_tic80): Define if ARCH_all is defined.
+ (disassembler): Add bfd_arch_tic80 support to set disassemble
+ to print_insn_tic80.
+ * tic80-dis.c (print_insn_tic80): Add stub.
+
+Fri Dec 27 22:30:57 1996 Fred Fish <fnf@cygnus.com>
+
+ * configure.in (arch in $selarchs): Add bfd_tic80_arch entry.
+ * configure: Regenerate with autoconf.
+ * tic80-dis.c: Add file.
+ * tic80-opc.c: Add file.
+
+end-sanitize-tic80
+start-sanitize-d10v
+Fri Dec 20 14:30:19 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
+
+ * d10v-opc.c (pre_defined_registers): Add cr[0-15], dpc, dpsw, link.
+
+end-sanitize-d10v
+Mon Dec 16 13:00:15 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_operands): Add SIMM16N.
+ (mn10200_opcodes): Use it for some logicals and btst insns.
+ Add "break" and "trap" instructions.
+
+ * mn10300-opc.c (mn10300_opcodes): Add "break" instruction.
+
+ * mn10200-opc.c: Add pseudo-ops for "mov (an),am" and "mov an,(am)".
+
+Sat Dec 14 22:36:20 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_mips16_insn_arg): The base address of a PC
+ relative load or add now depends upon whether the instruction is
+ in a delay slot.
+
+Wed Dec 11 09:23:46 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-dis.c: Finish writing disassembler.
+ * mn10200-opc.c (mn10200_opcodes): Fix mask for "mov imm8,dn".
+ Fix mask for "jmp (an)".
+
+ * mn10300-dis.c (disassemble, print_insn_mn10300): Corrently
+ handle endianness issues for mn10300.
+
+ * mn10200-opc.c (mn10200_opcodes): Fix operands for "movb dm,(an)".
+
+Tue Dec 10 12:08:05 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c (mn10200_opcodes): "mov imm8,d0" is a format 2
+ instruction. Fix opcode field for "movb (imm24),dn".
+
+ * mn10200-opc.c (mn10200_operands): Fix insertion position
+ for DI operand.
+
+Mon Dec 9 16:42:43 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10200-opc.c: Create mn10200 opcode table.
+ * mn10200-dis.c: Flesh out mn10200 disassembler. Not ready,
+ but moving along nicely.
+
+Sun Dec 8 04:28:31 1996 Peter Schauer (pes@regent.e-technik.tu-muenchen.de)
+
+ * Makefile.in (ALL_MACHINES): Add mips16-opc.o.
+
+Fri Dec 6 16:47:40 1996 J.T. Conklin <jtc@rhino.cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Revert change to use < and >
+ specifiers for fmovem* instructions.
+
+Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disassemble): Remove '$' register prefixing.
+
+Fri Dec 6 17:34:39 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips16-opc.c: Change opcode for entry/exit to avoid conflicting
+ with dsrl.
+
+Fri Dec 6 14:48:09 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c: Add some comments explaining the various
+ operands and such.
+
+ * mn10300-dis.c (disassemble): Fix minor gcc -Wall warnings.
+
+Thu Dec 5 12:09:48 1996 J.T. Conklin <jtc@rtl.cygnus.com>
+
+ * m68k-dis.c (print_insn_arg): Handle new < and > operand
+ specifiers.
+
+ * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
+ operand specifiers in fmovm* instructions.
+
+Wed Dec 4 14:52:18 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * ppc-opc.c (insert_li): Give an error if the offset has the two
+ least significant bits set.
+
+Wed Nov 27 13:09:01 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * mips-dis.c (print_insn_mips16): Separate the instruction from
+ the arguments with a tab, not a space.
+
+Tue Nov 26 13:24:17 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disasemble): Finish conversion to '$' as
+ register prefix.
+
+ * mn10300-opc.c (mn10300_opcodes): Fix mask field for
+ mov am,(imm32,sp).
+
+Tue Nov 26 10:53:21 1996 Ian Lance Taylor <ian@cygnus.com>
+
+ * configure: Rebuild with autoconf 2.12.
+
+ Add support for mips16 (16 bit MIPS implementation):
+ * mips16-opc.c: New file.
+ * mips-dis.c: Include "elf-bfd.h" and "elf/mips.h".
+ (mips16_reg_names): New static array.
+ (print_insn_big_mips): Use print_insn_mips16 in 16 bit mode or
+ after seeing a 16 bit symbol.
+ (print_insn_little_mips): Likewise.
+ (print_insn_mips16): New static function.
+ (print_mips16_insn_arg): New static function.
+ * mips-opc.c: Add jalx instruction.
+ * Makefile.in (mips16-opc.o): New target.
+ * configure.in: Use mips16-opc.o for bfd_mips_arch.
+ * configure: Rebuild.
+
+Mon Nov 25 16:15:17 1996 J.T. Conklin <jtc@cygnus.com>
+
+ * m68k-opc.c (m68k_opcodes): Simplify table by using < and >
+ operand specifiers in *save, *restore and movem* instructions.
+
+ * m68k-opc.c (m68k_opcodes): Fix move and movem instructions for
+ the coldfire.
+
+ * m68k-opc.c (m68k_opcodes): The coldfire (mcf5200) can only use
+ register operands for immediate arithmetic, not, neg, negx, and
+ set according to condition instructions.
+
+ * m68k-opc.c (m68k_opcodes): Consistantly Use "s" as the storage
+ specifier of the effective-address operand in immediate forms of
+ arithmetic instructions. The specifier for the immediate operand
+ notes how and where the constant will be stored.
+
+Mon Nov 25 11:17:01 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc"
+ opcode.
+
+ * mn10300-dis.c (disassemble): Use '$' instead of '%' for
+ register prefix.
+
+ * mn10300-dis.c (disassemble): Prefix registers with '%'.
+
+Wed Nov 20 10:37:13 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c (disassemble): Handle register lists.
+
+ * mn10300-opc.c: Fix handling of register list operand for
+ "call", "ret", and "rets" instructions.
+
+ * mn10300-dis.c (disassemble): Print PC-relative and memory
+ addresses symbolically if possible.
+ * mn10300-opc.c: Distinguish between absolute memory addresses,
+ pc-relative offsets & random immediates.
+
+ * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte
+ in 7 byte insns.
+ (disassemble): Handle SPLIT and EXTENDED operands.
+
+Tue Nov 19 13:33:01 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-dis.c: Rough cut at printing some operands.
+
+ * mn10300-dis.c: Start working on disassembler support.
+ * mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
+
+ * mn10300-opc.c (mn10300_operands): Add "REGS" for a register
+ list.
+ (mn10300_opcodes): Use REGS for register list in "movm" instructions.
+
+start-sanitize-d10v
+Mon Nov 18 15:20:35 1996 Michael Meissner <meissner@tiktok.cygnus.com>
+
+ * d10v-opc.c (d10v_opcodes): Add3 sets the carry.
+
+end-sanitize-d10v
+Fri Nov 15 13:43:19 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Demand parens around
+ register argument is calls and jmp instructions.
+
+Thu Nov 7 00:26:05 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and
+ getx operand. Fix opcode for mulqu imm,dn.
+
+Wed Nov 6 13:42:32 1996 Jeffrey A Law (law@cygnus.com)
+
+ * mn10300-opc.c (mn10300_operands): Hijack "bits" field
+ in MN10300_OPERAND_SPLIT operands for how many bits
+ appear in the basic insn word. Add IMM32_HIGH24,
+ IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
+ (mn10300_opcodes): Use new operands as needed.
+
+ * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8
+ for bset, bclr, btst instructions.
+ (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
+
+ * mn10300-opc.c (mn10300_operands): Remove many redundant
+ operands. Update opcode table as appropriate.
+ (IMM32): Add MN10300_OPERAND_SPLIT flag.
+ (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
+
Tue Nov 5 13:26:58 1996 Jeffrey A Law (law@cygnus.com)
* mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2
projects / deliverable / binutils-gdb.git / blobdiff