+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
+ vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
+ vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
+ vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
+ xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_xtp, extract_xtp): New functions.
+ (XTP, DQXP, DQXP_MASK): Define.
+ (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
+ (prefix_opcodes): Add plxvp and pstxvp.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
+ vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
+ vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
+ (L1OPT): Define.
+ (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
+
+2020-05-11 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (powerpc_init_dialect): Default to "power10".
+
+2020-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add "power10" entry.
+ (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
+ * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
+
+2020-05-11 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2020-04-30 Alex Coplan <alex.coplan@arm.com>
+
+ * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
+ * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
+ (operand_general_constraint_met_p): validate
+ AARCH64_OPND_UNDEFINED.
+ * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
+ for FLD_imm16_2.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
+ and SETRC insns.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ * po/sv.po: Updated Swedish translation.
+
+2020-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 22699
+ * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
+ IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
+ * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
+ IMM0_8U case.
+
+2020-04-21 Andreas Schwab <schwab@linux-m68k.org>
+
+ PR 25848
+ * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
+ cmpi only on m68020up and cpu32.
+
+2020-04-20 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_none): New.
+ * aarch64-asm.h (ins_none): New declaration.
+ * aarch64-dis.c (aarch64_ext_none): New.
+ * aarch64-dis.h (ext_none): New declaration.
+ * aarch64-opc.c (aarch64_print_operand): Update case for
+ AARCH64_OPND_BARRIER_PSB.
+ * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
+ (AARCH64_OPERANDS): Update inserter/extracter for
+ AARCH64_OPND_BARRIER_PSB to use new dummy functions.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-20 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
+ (aarch64_feature_ras, RAS): Likewise.
+ (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
+ (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
+ autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
+ autiaz, autiasp, autibz, autibsp to be CORE_INSN.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2020-04-17 Fredrik Strupe <fredrik@strupe.net>
+
+ * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
+ (print_insn_neon): Support disassembly of conditional
+ instructions.
+
+2020-02-16 David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-desc.h: Likewise.
+ * bpf-opc.c: Regenerate.
+ * bpf-opc.h: Likewise.
+
+2020-04-07 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
+ (prefix_table): New instructions (see prefixes above).
+ (rm_table): Likewise
+ * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
+ CPU_ANY_TSXLDTRK_FLAGS.
+ (cpu_flags): Add CpuTSXLDTRK.
+ * i386-opc.h (enum): Add CpuTSXLDTRK.
+ (i386_cpu_flags): Add cputsxldtrk.
+ * i386-opc.tbl: Add XSUSPLDTRK insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-04-02 Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (prefix_table): New instructions serialize.
+ * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
+ CPU_ANY_SERIALIZE_FLAGS.
+ (cpu_flags): Add CpuSERIALIZE.
+ * i386-opc.h (enum): Add CpuSERIALIZE.
+ (i386_cpu_flags): Add cpuserialize.
+ * i386-opc.tbl: Add SERIALIZE insns.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2020-03-26 Alan Modra <amodra@gmail.com>
+
+ * disassemble.h (opcodes_assert): Declare.
+ (OPCODES_ASSERT): Define.
+ * disassemble.c: Don't include assert.h. Include opintl.h.
+ (opcodes_assert): New function.
+ * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
+ (bfd_h8_disassemble): Reduce size of data array. Correctly
+ calculate maxlen. Omit insn decoding when insn length exceeds
+ maxlen. Exit from nibble loop when looking for E, before
+ accessing next data byte. Move processing of E outside loop.
+ Replace tests of maxlen in loop with assertions.
+
2020-03-26 Alan Modra <amodra@gmail.com>
* arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
projects / deliverable / binutils-gdb.git / blobdiff