Power10 128-bit binary integer operations

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e2cbe60cde1cc777a8142a73a5b0fa20c8548974..710504954c32a40898fcc7850cf9c5f4bcf82125 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,82 @@
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
+       vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
+       vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
+       vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
+       xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (insert_xtp, extract_xtp): New functions.
+       (XTP, DQXP, DQXP_MASK): Define.
+       (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
+       (prefix_opcodes): Add plxvp and pstxvp.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
+       vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
+       vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
+
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
+
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
+       (L1OPT): Define.
+       (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
+
+2020-05-11  Peter Bergner  <bergner@linux.ibm.com>
+
+       * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (powerpc_init_dialect): Default to "power10".
+
+2020-05-11  Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (ppc_opts): Add "power10" entry.
+       (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
+       * ppc-opc.c (POWER10): Rename from POWERXX.  Update all uses.
+
+2020-05-11  Nick Clifton  <nickc@redhat.com>
+
+       * po/fr.po: Updated French translation.
+
+2020-04-30  Alex Coplan  <alex.coplan@arm.com>
+
+       * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
+       * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
+       (operand_general_constraint_met_p): validate
+       AARCH64_OPND_UNDEFINED.
+       * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
+       for FLD_imm16_2.
+       * aarch64-asm-2.c: Regenerated.
+       * aarch64-dis-2.c: Regenerated.
+       * aarch64-opc-2.c: Regenerated.
+
+2020-04-29  Nick Clifton  <nickc@redhat.com>
+
+       PR 22699
+       * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
+       and SETRC insns.
+
+2020-04-29  Nick Clifton  <nickc@redhat.com>
+
+       * po/sv.po: Updated Swedish translation.
+
+2020-04-29  Nick Clifton  <nickc@redhat.com>
+
+       PR 22699
+       * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U.  Use
+       IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
+       * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
+       IMM0_8U case.
+
 2020-04-21  Andreas Schwab  <schwab@linux-m68k.org>
 
        PR 25848