+2019-12-04 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
+ forms.
+ (xbegin): Drop DefaultSize.
+ * i386-tbl.h: Re-generate.
+
+2019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
+
+ * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
+ Change the coproc CRC conditions to use the extension
+ feature set, second word, base on ARM_EXT2_CRC.
+
+2019-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
+ * i386-tbl.h: Re-generate.
+
+2019-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
+ JumpInterSegment, and JumpAbsolute entries.
+ * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
+ JUMP_ABSOLUTE): Define.
+ (struct i386_opcode_modifier): Extend jump field to 3 bits.
+ Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
+ fields.
+ * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
+ JumpInterSegment): Define.
+ * i386-tbl.h: Re-generate.
+
+2019-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_JUMPABSOLUTE entry.
+ (opcode_modifiers): Add JumpAbsolute entry.
+ (operand_types): Remove JumpAbsolute entry.
+ * i386-opc.h (JumpAbsolute): Move between enums.
+ (struct i386_opcode_modifier): Add jumpabsolute field.
+ (union i386_operand_type): Remove jumpabsolute field.
+ * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
+ * i386-init.h, i386-tbl.h: Re-generate.
+
+2019-11-14 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Add AnySize entry.
+ (operand_types): Remove AnySize entry.
+ * i386-opc.h (AnySize): Move between enums.
+ (struct i386_opcode_modifier): Add anysize field.
+ (OTUnused): Un-comment.
+ (union i386_operand_type): Remove anysize field.
+ * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
+ prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
+ bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
+ AnySize.
+ * i386-tbl.h: Re-generate.
+
+2019-11-12 Nelson Chu <nelson.chu@sifive.com>
+
+ * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
+ INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
+ use the floating point register (FPR).
+
2019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
* opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with