Add assembler and disassembler support for the new Armv8.4-a registers for AArch64.

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 7dcc29e0edfa5ebcb47bee38c6f948f48b011c90..809cad3117c51611ddee343ce2acc71411a614e5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,69 @@
+2017-11-09  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
+       dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
+       cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
+       sder32_el2, vncr_el2.
+       (aarch64_sys_reg_supported_p): Likewise.
+       (aarch64_pstatefields): Add dit register.
+       (aarch64_pstatefield_supported_p): Likewise.
+       (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
+       vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
+       vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
+       rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
+       rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
+       ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
+       rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
+
+2017-11-09  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
+       (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
+       (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
+       (QL_STLW, QL_STLX): New.
+
+2017-11-09  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-asm.h (ins_addr_offset): New.
+       * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
+       (aarch64_ins_addr_offset): New.
+       * aarch64-asm-2.c: Regenerate.
+       * aarch64-dis.h (ext_addr_offset): New.
+       * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
+       (aarch64_ext_addr_offset): New.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
+       FLD_imm4_2 and FLD_SM3_imm2.
+       * aarch64-opc.c (fields): Add FLD_imm6_2,
+       FLD_imm4_2 and FLD_SM3_imm2.
+       (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
+       (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+       AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
+       * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
+       * aarch64-tbl.h
+       (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
+
+2017-11-09 Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-tbl.h
+       (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
+       (aarch64_feature_sm4, aarch64_feature_sha3): New.
+       (aarch64_feature_fp_16_v8_2): New.
+       (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
+       (V8_4_INSN, CRYPTO_V8_2_INSN): New.
+       (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
+
+2017-11-08  Tamar Christina  <tamar.christina@arm.com>
+
+       * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
+       (aarch64_feature_sha2, aarch64_feature_aes): New.
+       (SHA2, AES): New.
+       (AES_INSN, SHA2_INSN): New.
+       (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
+       (sha1h, sha1su1, sha256su0, sha1c, sha1p,
+        sha1m, sha1su0, sha256h, sha256h2, sha256su1):
+       Change to SHA2_INS.
+
 2017-11-08  Jiong Wang  <jiong.wang@arm.com>
            Tamar Christina <tamar.christina@arm.com>