+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
+ dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
+ cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
+ sder32_el2, vncr_el2.
+ (aarch64_sys_reg_supported_p): Likewise.
+ (aarch64_pstatefields): Add dit register.
+ (aarch64_pstatefield_supported_p): Likewise.
+ (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
+ vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
+ vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
+ rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
+ rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
+ ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
+ rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
+ (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
+ (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
+ (QL_STLW, QL_STLX): New.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.h (ins_addr_offset): New.
+ * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
+ (aarch64_ins_addr_offset): New.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis.h (ext_addr_offset): New.
+ * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
+ (aarch64_ext_addr_offset): New.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ * aarch64-opc.c (fields): Add FLD_imm6_2,
+ FLD_imm4_2 and FLD_SM3_imm2.
+ (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
+ (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
+ AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
+ * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
+ * aarch64-tbl.h
+ (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
+
+2017-11-09 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h
+ (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
+ (aarch64_feature_sm4, aarch64_feature_sha3): New.
+ (aarch64_feature_fp_16_v8_2): New.
+ (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
+ (V8_4_INSN, CRYPTO_V8_2_INSN): New.
+ (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
+
+2017-11-08 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
+ (aarch64_feature_sha2, aarch64_feature_aes): New.
+ (SHA2, AES): New.
+ (AES_INSN, SHA2_INSN): New.
+ (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
+ (sha1h, sha1su1, sha256su0, sha1c, sha1p,
+ sha1m, sha1su0, sha256h, sha256h2, sha256su1):
+ Change to SHA2_INS.
+
+2017-11-08 Jiong Wang <jiong.wang@arm.com>
+ Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
+ FP16 instructions, including vfmal.f16 and vfmsl.f16.
+
+2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
+
+2017-11-07 Alan Modra <amodra@gmail.com>
+
+ * opintl.h: Formatting, comment fixes.
+ (gettext, ngettext): Redefine when ENABLE_NLS.
+ (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
+ (_): Define using gettext.
+ (textdomain, bindtextdomain): Use safer "do nothing".
+
+2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_hex): New variable.
+ (parse_option): Check for hex option.
+ (print_insn_arc): Use hexadecimal representation for short
+ immediate values when requested.
+ (print_arc_disassembler_options): Add hex option to the list.
+
+2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
+ (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
+ (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
+ (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
+ (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
+ (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
+ (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
+ (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
+ (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
+ (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
+ (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
+ (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
+ (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
+ (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
+ (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
+ (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
+ (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
+ (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
+ (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
+ Changed opcodes.
+ (prealloc, prefetch*): Place them before ld instruction.
+ * arc-opc.c (skip_this_opcode): Add ARITH class.
+
+2017-10-25 Alan Modra <amodra@gmail.com>
+
+ PR 22348
+ * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
+ (cr16_words, cr16_allWords, processing_argument_number): Likewise.
+ (imm4flag, size_changed): Likewise.
+ * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
+ (words, allWords, processing_argument_number): Likewise.
+ (cst4flag, size_changed): Likewise.
+ * crx-opc.c (crx_cst4_map): Rename from cst4_map.
+ (crx_cst4_maps): Rename from cst4_maps.
+ (crx_no_op_insn): Rename from no_op_insn.
+
+2017-10-24 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (match_c_addi16sp) : New function.
+ (match_c_addi4spn): New function.
+ (match_c_lui): Don't allow 0-immediate encodings.
+ (riscv_opcodes) <addi>: Use the above functions.
+ <add>: Likewise.
+ <c.addi4spn>: Likewise.
+ <c.addi16sp>: Likewise.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-init.h: Regenerate
+ * i386-tbl.h: Likewise
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
+ (enum): Add EVEX_W_0F3854_P_2.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
+ CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_BITALG.
+ * i386-opc.h (enum): Add CpuAVX512_BITALG.
+ (i386_cpu_flags): Add cpuavx512_bitalg..
+ * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
+ CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VNNI.
+ * i386-opc.h (enum): Add CpuAVX512_VNNI.
+ (i386_cpu_flags): Add cpuavx512_vnni.
+ * i386-opc.tbl Add Intel AVX512_VNNI instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
+ (enum): Remove VEX_LEN_0F3A44_P_2.
+ (vex_len_table): Ditto.
+ (enum): Remove VEX_W_0F3A44_P_2.
+ (vew_w_table): Ditto.
+ (prefix_table): Adjust instructions (see prefixes above).
+ * i386-dis-evex.h (evex_table):
+ Add new instructions (see prefixes above).
+ * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
+ (bitfield_cpu_flags): Ditto.
+ * i386-opc.h (enum): Ditto.
+ (i386_cpu_flags): Ditto.
+ (CpuUnused): Comment out to avoid zero-width field problem.
+ * i386-opc.tbl (vpclmulqdq): New instruction.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
+ PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
+ (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
+ VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
+ (vex_len_table): Ditto.
+ (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
+ VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
+ (vew_w_table): Ditto.
+ (prefix_table): Adjust instructions (see prefixes above).
+ * i386-dis-evex.h (evex_table):
+ Add new instructions (see prefixes above).
+ * i386-gen.c (cpu_flag_init): Add VAES.
+ (bitfield_cpu_flags): Ditto.
+ * i386-opc.h (enum): Ditto.
+ (i386_cpu_flags): Ditto.
+ * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
+ PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
+ PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
+ (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
+ EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
+ (prefix_table): Updated (see prefixes above).
+ (three_byte_table): Likewise.
+ (vex_w_table): Likewise.
+ * i386-dis-evex.h: Likewise.
+ * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
+ (cpu_flags): Add CpuGFNI.
+ * i386-opc.h (enum): Add CpuGFNI.
+ (i386_cpu_flags): Add cpugfni.
+ * i386-opc.tbl: Add Intel GFNI instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
+ Define EXbScalar and EXwScalar for OP_EX.
+ (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
+ PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
+ PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
+ PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
+ (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
+ EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
+ EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
+ EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
+ (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
+ (OP_E_memory): Likewise.
+ * i386-dis-evex.h: Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
+ CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_VBMI2.
+ * i386-opc.h (enum): Add CpuAVX512_VBMI2.
+ (i386_cpu_flags): Add cpuavx512_vbmi2.
+ * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Likewise.
+
+2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
+
+ * visium-dis.c (disassem_class1) <case 0>: Print the operands.
+
+2017-10-12 James Bowman <james.bowman@ftdichip.com>
+
+ * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
+ * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
+ K15. Add jmpix pattern.
+
+2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-opc.txt (prno, tpei, irbm): New instructions added.
+
+2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
+
+ * s390-opc.c (INSTR_SI_RD): New macro.
+ (INSTR_S_RD): Adjust example instruction.
+ * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
+ SI_RD.
+
+2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
+
+ * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
+ e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
+ VLE multimple load/store instructions. Old e_ldm* variants are
+ kept as aliases.
+ Add missing e_lmvmcsrrw and e_stmvmcsrrw.
+
+2017-09-27 Nick Clifton <nickc@redhat.com>
+
+ PR 22179
+ * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
+ names for the fmv.x.s and fmv.s.x instructions respectively.
+
+2017-09-26 do <do@nerilex.org>
+
+ PR 22123
+ * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
+ be used on CPUs that have emacs support.
+
+2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
+
+ * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
+
+2017-09-09 Kamil Rytarowski <n54@gmx.com>
+
+ * nds32-asm.c: Rename __BIT() to N32_BIT().
+ * nds32-asm.h: Likewise.
+ * nds32-dis.c: Likewise.
+
+2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (last_active_prefix): Removed.
+ (ckprefix): Don't set last_active_prefix.
+ (NOTRACK_Fixup): Don't check last_active_prefix.
+
+2017-08-31 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2017-08-31 James Bowman <james.bowman@ftdichip.com>
+
+ * ft32-dis.c (print_insn_ft32): Correct display of non-address
+ fields.
+
+2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
+ PPC_OPCODE_EFS2 flag to "e200z4" entry.
+ New entries efs2 and spe2.
+ Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
+ (SPE2_OPCD_SEGS): New macro.
+ (spe2_opcd_indices): New.
+ (disassemble_init_powerpc): Handle SPE2 opcodes.
+ (lookup_spe2): New function.
+ (print_insn_powerpc): call lookup_spe2.
+ * ppc-opc.c (insert_evuimm1_ex0): New function.
+ (extract_evuimm1_ex0): Likewise.
+ (insert_evuimm_lt8): Likewise.
+ (extract_evuimm_lt8): Likewise.
+ (insert_off_spe2): Likewise.
+ (extract_off_spe2): Likewise.
+ (insert_Ddd): Likewise.
+ (extract_Ddd): Likewise.
+ (DD): New operand.
+ (EVUIMM_LT8): Likewise.
+ (EVUIMM_LT16): Adjust.
+ (MMMM): New operand.
+ (EVUIMM_1): Likewise.
+ (EVUIMM_1_EX0): Likewise.
+ (EVUIMM_2): Adjust.
+ (NNN): New operand.
+ (VX_OFF_SPE2): Likewise.
+ (BBB): Likewise.
+ (DDD): Likewise.
+ (VX_MASK_DDD): New mask.
+ (HH): New operand.
+ (VX_RA_CONST): New macro.
+ (VX_RA_CONST_MASK): Likewise.
+ (VX_RB_CONST): Likewise.
+ (VX_RB_CONST_MASK): Likewise.
+ (VX_OFF_SPE2_MASK): Likewise.
+ (VX_SPE_CRFD): Likewise.
+ (VX_SPE_CRFD_MASK VX): Likewise.
+ (VX_SPE2_CLR): Likewise.
+ (VX_SPE2_CLR_MASK): Likewise.
+ (VX_SPE2_SPLATB): Likewise.
+ (VX_SPE2_SPLATB_MASK): Likewise.
+ (VX_SPE2_OCTET): Likewise.
+ (VX_SPE2_OCTET_MASK): Likewise.
+ (VX_SPE2_DDHH): Likewise.
+ (VX_SPE2_DDHH_MASK): Likewise.
+ (VX_SPE2_HH): Likewise.
+ (VX_SPE2_HH_MASK): Likewise.
+ (VX_SPE2_EVMAR): Likewise.
+ (VX_SPE2_EVMAR_MASK): Likewise.
+ (PPCSPE2): Likewise.
+ (PPCEFS2): Likewise.
+ (vle_opcodes): Add EFS2 and some missing SPE opcodes.
+ (powerpc_macros): Map old SPE instructions have new names
+ with the same opcodes. Add SPE2 instructions which just are
+ mapped to SPE2.
+ (spe2_opcodes): Add SPE2 opcodes.
+
+2017-08-23 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c: Formatting and comment fixes. Move insert and
+ extract functions earlier, deleting forward declarations.
+ (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
+ RA_MASK.
+
+2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
+
+ * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
+
+2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
+ Edmar Wienskoski <edmar.wienskoski@nxp.com>
+
+ * ppc-opc.c (insert_evuimm2_ex0): New function.
+ (extract_evuimm2_ex0): Likewise.
+ (insert_evuimm4_ex0): Likewise.
+ (extract_evuimm4_ex0): Likewise.
+ (insert_evuimm8_ex0): Likewise.
+ (extract_evuimm8_ex0): Likewise.
+ (insert_evuimm_lt16): Likewise.
+ (extract_evuimm_lt16): Likewise.
+ (insert_rD_rS_even): Likewise.
+ (extract_rD_rS_even): Likewise.
+ (insert_off_lsp): Likewise.
+ (extract_off_lsp): Likewise.
+ (RD_EVEN): New operand.
+ (RS_EVEN): Likewise.
+ (RSQ): Adjust.
+ (EVUIMM_LT16): New operand.
+ (HTM_SI): Adjust.
+ (EVUIMM_2_EX0): New operand.
+ (EVUIMM_4): Adjust.
+ (EVUIMM_4_EX0): New operand.
+ (EVUIMM_8): Adjust.
+ (EVUIMM_8_EX0): New operand.
+ (WS): Adjust.
+ (VX_OFF): New operand.
+ (VX_LSP): New macro.
+ (VX_LSP_MASK): Likewise.
+ (VX_LSP_OFF_MASK): Likewise.
+ (PPC_OPCODE_LSP): Likewise.
+ (vle_opcodes): Add LSP opcodes.
+ * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
+
+2017-08-09 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
+ register operands in CRC instructions.
+ (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
+ comments.
+
+2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * disassemble.c (disassembler): Mark big and mach with
+ ATTRIBUTE_UNUSED.
+
+2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * disassemble.c (disassembler): Remove arch/mach/endian
+ assertions.
+
+2017-07-25 Nick Clifton <nickc@redhat.com>
+
+ PR 21739
+ * arc-opc.c (insert_rhv2): Use lower case first letter in error
+ message.
+ (insert_r0): Likewise.
+ (insert_r1): Likewise.
+ (insert_r2): Likewise.
+ (insert_r3): Likewise.
+ (insert_sp): Likewise.
+ (insert_gp): Likewise.
+ (insert_pcl): Likewise.
+ (insert_blink): Likewise.
+ (insert_ilink1): Likewise.
+ (insert_ilink2): Likewise.
+ (insert_ras): Likewise.
+ (insert_rbs): Likewise.
+ (insert_rcs): Likewise.
+ (insert_simm3s): Likewise.
+ (insert_rrange): Likewise.
+ (insert_r13el): Likewise.
+ (insert_fpel): Likewise.
+ (insert_blinkel): Likewise.
+ (insert_pclel): Likewise.
+ (insert_nps_bitop_size_2b): Likewise.
+ (insert_nps_imm_offset): Likewise.
+ (insert_nps_imm_entry): Likewise.
+ (insert_nps_size_16bit): Likewise.
+ (insert_nps_##NAME##_pos): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_bitop_ins_ext): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_min_hofs): Likewise.
+ (insert_nps_##NAME): Likewise.
+ (insert_nps_rbdouble_64): Likewise.
+ (insert_nps_misc_imm_offset): Likewise.
+ * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
+ option description.
+
+2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
+ Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
+ correct the print.
+ * aarch64-dis-2.c: Regenerated.
+
+2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
+ table.
+
+2017-07-20 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-regs.h (sec_stat): New aux register.
+ (aux_kernel_sp): Likewise.
+ (aux_sec_u_sp): Likewise.
+ (aux_sec_k_sp): Likewise.
+ (sec_vecbase_build): Likewise.
+ (nsc_table_top): Likewise.
+ (nsc_table_base): Likewise.
+ (ersec_stat): Likewise.
+ (aux_sec_except): Likewise.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (extract_uimm12_20): New function.
+ (UIMM12_20): New operand.
+ (SIMM3_5_S): Adjust.
+ * arc-tbl.h (sjli): Add new instruction.
+
+2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
+ John Eric Martin <John.Martin@emmicro-us.com>
+
+ * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
+ (UIMM3_23): Adjust accordingly.
+ * arc-regs.h: Add/correct jli_base register.
+ * arc-tbl.h (jli_s): Likewise.
+
+2017-07-18 Nick Clifton <nickc@redhat.com>
+
+ PR 21775
+ * aarch64-opc.c: Fix spelling typos.
+ * i386-dis.c: Likewise.
+
+2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
+
+ * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
+ max_addr_offset and octets variables to size_t.
+
+2017-07-12 Alan Modra <amodra@gmail.com>
+
+ * po/da.po: Update from translationproject.org/latest/opcodes/.
+ * po/de.po: Likewise.
+ * po/es.po: Likewise.
+ * po/fi.po: Likewise.
+ * po/fr.po: Likewise.
+ * po/id.po: Likewise.
+ * po/it.po: Likewise.
+ * po/nl.po: Likewise.
+ * po/pt_BR.po: Likewise.
+ * po/ro.po: Likewise.
+ * po/sv.po: Likewise.
+ * po/tr.po: Likewise.
+ * po/uk.po: Likewise.
+ * po/vi.po: Likewise.
+ * po/zh_CN.po: Likewise.
+
+2017-07-11 Yao Qi <yao.qi@linaro.org>
+ Alan Modra <amodra@gmail.com>
+
+ * cgen.sh: Mark generated files read-only.
+ * epiphany-asm.c: Regenerate.
+ * epiphany-desc.c: Regenerate.
+ * epiphany-desc.h: Regenerate.
+ * epiphany-dis.c: Regenerate.
+ * epiphany-ibld.c: Regenerate.
+ * epiphany-opc.c: Regenerate.
+ * epiphany-opc.h: Regenerate.
+ * fr30-asm.c: Regenerate.
+ * fr30-desc.c: Regenerate.
+ * fr30-desc.h: Regenerate.
+ * fr30-dis.c: Regenerate.
+ * fr30-ibld.c: Regenerate.
+ * fr30-opc.c: Regenerate.
+ * fr30-opc.h: Regenerate.
+ * frv-asm.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * frv-desc.h: Regenerate.
+ * frv-dis.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * frv-opc.c: Regenerate.
+ * frv-opc.h: Regenerate.
+ * ip2k-asm.c: Regenerate.
+ * ip2k-desc.c: Regenerate.
+ * ip2k-desc.h: Regenerate.
+ * ip2k-dis.c: Regenerate.
+ * ip2k-ibld.c: Regenerate.
+ * ip2k-opc.c: Regenerate.
+ * ip2k-opc.h: Regenerate.
+ * iq2000-asm.c: Regenerate.
+ * iq2000-desc.c: Regenerate.
+ * iq2000-desc.h: Regenerate.
+ * iq2000-dis.c: Regenerate.
+ * iq2000-ibld.c: Regenerate.
+ * iq2000-opc.c: Regenerate.
+ * iq2000-opc.h: Regenerate.
+ * lm32-asm.c: Regenerate.
+ * lm32-desc.c: Regenerate.
+ * lm32-desc.h: Regenerate.
+ * lm32-dis.c: Regenerate.
+ * lm32-ibld.c: Regenerate.
+ * lm32-opc.c: Regenerate.
+ * lm32-opc.h: Regenerate.
+ * lm32-opinst.c: Regenerate.
+ * m32c-asm.c: Regenerate.
+ * m32c-desc.c: Regenerate.
+ * m32c-desc.h: Regenerate.
+ * m32c-dis.c: Regenerate.
+ * m32c-ibld.c: Regenerate.
+ * m32c-opc.c: Regenerate.
+ * m32c-opc.h: Regenerate.
+ * m32r-asm.c: Regenerate.
+ * m32r-desc.c: Regenerate.
+ * m32r-desc.h: Regenerate.
+ * m32r-dis.c: Regenerate.
+ * m32r-ibld.c: Regenerate.
+ * m32r-opc.c: Regenerate.
+ * m32r-opc.h: Regenerate.
+ * m32r-opinst.c: Regenerate.
+ * mep-asm.c: Regenerate.
+ * mep-desc.c: Regenerate.
+ * mep-desc.h: Regenerate.
+ * mep-dis.c: Regenerate.
+ * mep-ibld.c: Regenerate.
+ * mep-opc.c: Regenerate.
+ * mep-opc.h: Regenerate.
+ * mt-asm.c: Regenerate.
+ * mt-desc.c: Regenerate.
+ * mt-desc.h: Regenerate.
+ * mt-dis.c: Regenerate.
+ * mt-ibld.c: Regenerate.
+ * mt-opc.c: Regenerate.
+ * mt-opc.h: Regenerate.
+ * or1k-asm.c: Regenerate.
+ * or1k-desc.c: Regenerate.
+ * or1k-desc.h: Regenerate.
+ * or1k-dis.c: Regenerate.
+ * or1k-ibld.c: Regenerate.
+ * or1k-opc.c: Regenerate.
+ * or1k-opc.h: Regenerate.
+ * or1k-opinst.c: Regenerate.
+ * xc16x-asm.c: Regenerate.
+ * xc16x-desc.c: Regenerate.
+ * xc16x-desc.h: Regenerate.
+ * xc16x-dis.c: Regenerate.
+ * xc16x-ibld.c: Regenerate.
+ * xc16x-opc.c: Regenerate.
+ * xc16x-opc.h: Regenerate.
+ * xstormy16-asm.c: Regenerate.
+ * xstormy16-desc.c: Regenerate.
+ * xstormy16-desc.h: Regenerate.
+ * xstormy16-dis.c: Regenerate.
+ * xstormy16-ibld.c: Regenerate.
+ * xstormy16-opc.c: Regenerate.
+ * xstormy16-opc.h: Regenerate.
+
+2017-07-07 Alan Modra <amodra@gmail.com>
+
+ * cgen-dis.in: Include disassemble.h, not dis-asm.h.
+ * m32c-dis.c: Regenerate.
+ * mep-dis.c: Regenerate.
+
+2017-07-05 Borislav Petkov <bp@suse.de>
+
+ * i386-dis.c: Enable ModRM.reg /6 aliases.
+
+2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * opcodes/arm-dis.c: Support MVFR2 in disassembly
+ with vmrs and vmsr.
+
+2017-07-04 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2017-07-03 Tristan Gingold <gingold@adacore.com>
+
+ * po/opcodes.pot: Regenerate.
+
+2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
+ entries to the MSA ASE instruction block.
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
+ * micromips-opc.c (XPA, XPAVZ): New macros.
+ (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
+ "mthgc0".
+
+2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
+ Maciej W. Rozycki <macro@imgtec.com>
+
+ * micromips-opc.c (I36): New macro.
+ (micromips_opcodes): Add "eretnc".
+
+2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
+ Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): Handle the
+ ASE_XPA_VIRT flag.
+ (parse_mips_ase_option): New function.
+ (parse_mips_dis_option): Factor out ASE option handling to the
+ new function. Call `mips_calculate_combination_ases'.
+ * mips-opc.c (XPAVZ): New macro.
+ (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
+ "mfhgc0", "mthc0" and "mthgc0".
+
+2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): New function.
+ (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
+ calculation to the new function.
+ (set_default_mips_dis_options): Call the new function.
+
+2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (parse_disassembler_options): Use
+ FOR_EACH_DISASSEMBLER_OPTION.
+
+2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
+
+ * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
+ disassembler option strings.
+ (parse_cpu_option): Likewise.
+
+2017-06-28 Tamar Christina <tamar.christina@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
+ * aarch64-dis.c (aarch64_ext_reglane): Likewise.
+ * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
+ (aarch64_feature_dotprod, DOT_INSN): New.
+ (udot, sdot): New.
+ * aarch64-dis-2.c: Regenerated.
+
+2017-06-28 Jiong Wang <jiong.wang@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
+
+2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+ Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips-formats.h (INT_BIAS): New macro.
+ (INT_ADJ): Redefine in INT_BIAS terms.
+ * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
+ (mips_print_save_restore): New function.
+ (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
+ (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
+ call.
+ (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
+ (print_mips16_insn_arg): Call `mips_print_save_restore' for
+ OP_SAVE_RESTORE_LIST handling, factored out from here.
+ * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
+ (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
+ (mips_builtin_opcodes): Add "restore" and "save" entries.
+ * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
+ (IAMR2): New macro.
+ (mips16_opcodes): Add "copyw" and "ucopyw" entries.
+
+2017-06-23 Andrew Waterman <andrew@sifive.com>
+
+ * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
+ alias; do not mark SLTI instruction as an alias.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (RM_0FAE_REG_5): Removed.
+ (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
+ (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
+ (PREFIX_MOD_3_0FAE_REG_5): Likewise.
+ (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
+ PREFIX_MOD_3_0F01_REG_5_RM_0.
+ (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
+ PREFIX_MOD_3_0FAE_REG_5.
+ (mod_table): Update MOD_0FAE_REG_5.
+ (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
+ * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
+ * i386-tbl.h: Regenerated.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
+ * i386-opc.tbl: Likewise.
+ * i386-tbl.h: Regenerated.
+
+2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
+ and "jmp{&|}".
+ (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
+ prefix.
+
+2017-06-19 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21614
+ * score-dis.c (score_opcodes): Add sentinel.
+
+2017-06-16 Alan Modra <amodra@gmail.com>
+
+ * rx-decode.c: Regenerate.
+
+2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/21594
+ * i386-dis.c (OP_E_register): Check valid bnd register.
+ (OP_G): Likewise.
+
+2017-06-15 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21595
+ * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
+ range value.
+
+2017-06-15 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21588
+ * rl78-decode.opc (OP_BUF_LEN): Define.
+ (GETBYTE): Check for the index exceeding OP_BUF_LEN.
+ (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
+ array.
+ * rl78-decode.c: Regenerate.
+
+2017-06-15 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21586
+ * bfin-dis.c (gregs): Clip index to prevent overflow.
+ (regs): Likewise.
+ (regs_lo): Likewise.
+ (regs_hi): Likewise.
+
+2017-06-14 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21576
+ * score7-dis.c (score_opcodes): Add sentinel.
+
+2017-06-14 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
+ * arm-dis.c: Likewise.
+ * ia64-dis.c: Likewise.
+ * mips-dis.c: Likewise.
+ * spu-dis.c: Likewise.
+ * disassemble.h (print_insn_aarch64): New declaration, moved from
+ include/dis-asm.h.
+ (print_insn_big_arm, print_insn_big_mips): Likewise.
+ (print_insn_i386, print_insn_ia64): Likewise.
+ (print_insn_little_arm, print_insn_little_mips): Likewise.
+
+2017-06-14 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/21587
+ * rx-decode.opc: Include libiberty.h
+ (GET_SCALE): New macro - validates access to SCALE array.
+ (GET_PSCALE): New macro - validates access to PSCALE array.
+ (DIs, SIs, S2Is, rx_disp): Use new macros.
+ * rx-decode.c: Regenerate.
+
+2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
+
+2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
+
+ * arc-dis.c (enforced_isa_mask): Declare.
+ (cpu_types): Likewise.
+ (parse_cpu_option): New function.
+ (parse_disassembler_options): Use it.
+ (print_insn_arc): Use enforced_isa_mask.
+ (print_arc_disassembler_options): Document new options.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * alpha-dis.c: Include disassemble.h, don't include
+ dis-asm.h.
+ * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
+ * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
+ * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
+ * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
+ * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
+ * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
+ * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
+ * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
+ * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
+ * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
+ * moxie-dis.c, msp430-dis.c, mt-dis.c:
+ * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
+ * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
+ * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
+ * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
+ * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
+ * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
+ * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
+ * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
+ * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
+ * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
+ * z80-dis.c, z8k-dis.c: Likewise.
+ * disassemble.h: New file.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * rl78-dis.c (rl78_get_disassembler): If parameter abfd
+ is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
+
+2017-05-24 Yao Qi <yao.qi@linaro.org>
+
+ * disassemble.c (disassembler): Add arguments a, big and mach.
+ Use them.
+
+2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (NOTRACK_Fixup): New.
+ (NOTRACK): Likewise.
+ (NOTRACK_PREFIX): Likewise.
+ (last_active_prefix): Likewise.
+ (reg_table): Use NOTRACK on indirect call and jmp.
+ (ckprefix): Set last_active_prefix.
+ (prefix_name): Return "notrack" for NOTRACK_PREFIX.
+ * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
+ * i386-opc.h (NoTrackPrefixOk): New.
+ (i386_opcode_modifier): Add notrackprefixok.
+ * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
+ Add notrack.
+ * i386-tbl.h: Regenerated.
+
+2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
+ (X_IMM2): Define.
+ (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
+ bfd_mach_sparc_v9m8.
+ (print_insn_sparc): Handle new operand types.
+ * sparc-opc.c (MASK_M8): Define.
+ (v6): Add MASK_M8.
+ (v6notlet): Likewise.
+ (v7): Likewise.
+ (v8): Likewise.
+ (v9): Likewise.
+ (v9a): Likewise.
+ (v9b): Likewise.
+ (v9c): Likewise.
+ (v9d): Likewise.
+ (v9e): Likewise.
+ (v9v): Likewise.
+ (v9m): Likewise.
+ (v9andleon): Likewise.
+ (m8): Define.
+ (HWS_VM8): Define.
+ (HWS2_VM8): Likewise.
+ (sparc_opcode_archs): Add entry for "m8".
+ (sparc_opcodes): Add OSA2017 and M8 instructions
+ dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
+ fpx{ll,ra,rl}64x,
+ ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
+ ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
+ revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
+ stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
+ (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
+ ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
+ ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
+ ASI_CORE_SELECT_COMMIT_NHT.
+
+2017-05-18 Alan Modra <amodra@gmail.com>
+
+ * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
+ * aarch64-dis.c: Likewise.
+ * aarch64-gen.c: Likewise.
+ * aarch64-opc.c: Likewise.
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
+ ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
+ (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
+ (print_insn_arg) <OP_REG28>: Add handler.
+ (validate_insn_args) <OP_REG28>: Handle.
+ (print_mips16_insn_arg): Handle MIPS16 instructions that require
+ 32-bit encoding and 9-bit immediates.
+ (print_insn_mips16): Handle MIPS16 instructions that require
+ 32-bit encoding and MFC0/MTC0 operand decoding.
+ * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
+ <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
+ (RD_C0, WR_C0, E2, E2MT): New macros.
+ (mips16_opcodes): Add entries for MIPS16e2 instructions:
+ GP-relative "addiu" and its "addu" spelling, "andi", "cache",
+ "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
+ "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
+ "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
+ "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
+ instructions, "swl", "swr", "sync" and its "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
+ "xori", "dmt", "dvpe", "emt" and "evpe". Add split
+ regular/extended entries for original MIPS16 ISA revision
+ instructions whose extended forms are subdecoded in the MIPS16e2
+ ISA revision: "li", "sll" and "srl".
+
+2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
+ reference in CP0 move operand decoding.
+
+2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
+ type to hexadecimal.
+ (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
+
+2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
+ "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
+ "sync_rmb" and "sync_wmb" as aliases.
+ * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
+ "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
+
+2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (parse_option): Update quarkse_em option..
+ * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
+ QUARKSE1.
+ (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
+
+2017-05-03 Kito Cheng <kito.cheng@gmail.com>
+
+ * riscv-dis.c (print_insn_args): Handle 'Co' operands.
+
+2017-05-01 Michael Clark <michaeljclark@mac.com>
+
+ * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
+ register.
+
+2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
+ and branches and not synthetic data instructions.
+
+2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
+
+ * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
+
+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
+ * arc-opc.c (insert_r13el): New function.
+ (R13_EL): Define.
+ * arc-tbl.h: Add new enter/leave variants.
+
+2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
+
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips_disassembler_options): Add
+ `no-aliases'.
+
+2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (AL): New macro.
+ (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
+ of "ld" and "lw" as aliases.
+
2017-04-24 Tamar Christina <tamar.christina@arm.com>
* aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
projects / deliverable / binutils-gdb.git / blobdiff