Include bfd_stdint.h in bfd.h

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 47873949c7ceb3a9de3621330fb40ad99c5a0eb9..8676f5f3b525a2fde3d898a848628f8a77db224f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,47 @@
+2018-12-18  Alan Modra  <amodra@gmail.com>
+
+       * arm-dis.c: Include bfd.h.
+       * aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
+       * csky-dis.c: Likewise.
+       * nds32-asm.c: Likewise.
+       * riscv-dis.c: Likewise.
+       * s12z-dis.c: Likewise.
+       * wasm32-dis.c: Likewise.
+
+2018-12-07  Jim Wilson  <jimw@sifive.com>
+
+       PR gas/23956
+       * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
+
+2018-12-06  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * configure.ac (enable-cgen-maint): Support passing path to cgen
+       source tree.
+       * configure: Regenerate.
+
+2018-12-06  Andrew Burgess  <andrew.burgess@embecosm.com>
+
+       * disassembler.c (disassemble_init_for_target): Add RISC-V
+       initialisation.
+       * riscv-dis.c (riscv_symbol_is_valid): New function.
+
+2018-12-03  Kito Cheng <kito@andestech.com>
+
+       * riscv-opc.c: Change the type of xlen, because type of
+       xlen_requirement changed.
+
+2018-12-03  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+       PR 23193
+        PR 19721
+        * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
+       encoding as MOV if the shift operation is a left shift of zero.
+
+2018-11-29  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
+       (c.unimp): New.
+
 2018-11-27  Jim Wilson  <jimw@sifive.com>
 
        * riscv-opc.c (ciw): Fix whitespace to align columns.