+2018-12-18 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c: Include bfd.h.
+ * aarch64-opc.c: Include bfd_stdint.h rather than stdint.h.
+ * csky-dis.c: Likewise.
+ * nds32-asm.c: Likewise.
+ * riscv-dis.c: Likewise.
+ * s12z-dis.c: Likewise.
+ * wasm32-dis.c: Likewise.
+
+2018-12-07 Jim Wilson <jimw@sifive.com>
+
+ PR gas/23956
+ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
+
+2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * configure.ac (enable-cgen-maint): Support passing path to cgen
+ source tree.
+ * configure: Regenerate.
+
+2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * disassembler.c (disassemble_init_for_target): Add RISC-V
+ initialisation.
+ * riscv-dis.c (riscv_symbol_is_valid): New function.
+
+2018-12-03 Kito Cheng <kito@andestech.com>
+
+ * riscv-opc.c: Change the type of xlen, because type of
+ xlen_requirement changed.
+
+2018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
+
+ PR 23193
+ PR 19721
+ * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
+ encoding as MOV if the shift operation is a left shift of zero.
+
+2018-11-29 Jim Wilson <jimw@sifive.com>
+
+ * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
+ (c.unimp): New.
+
+2018-11-27 Jim Wilson <jimw@sifive.com>
+
+ * riscv-opc.c (ciw): Fix whitespace to align columns.
+ (ca): New.
+
+2018-11-21 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
+ if the postbyte matches the appropriate pattern.
+
+2018-11-13 Francois H. Theron <francois.theron@netronome.com>
+
+ * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
+ IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
+ IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
+ CIGDVAC and GZVA.
+ (aarch64_sys_ins_reg_supported_p): New check for above.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
+ TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
+ RGSR_EL1 and GCR_EL1.
+ (aarch64_sys_reg_supported_p): New check for above.
+ (aarch64_pstatefields): New entry for TCO.
+ (aarch64_pstatefield_supported_p): New check for above.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
+ * aarch64-asm.h (ins_addr_simple_2): Declare the above.
+ * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
+ * aarch64-dis.h (ext_addr_simple_2): Declare the above.
+ * aarch64-opc.c (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
+ (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
+ * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
+ (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (QL_LDG): New.
+ (aarch64_opcode_table): Add ldg.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
+ for AARCH64_OPND_QLF_imm_tag.
+ (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
+ (aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
+ (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
+ for both offset and pre/post indexed versions.
+ (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
+ (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
+ * aarch64-opc.c (fields): Add entry for imm4_3.
+ (operand_general_constraint_met_p): Add cases for
+ AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
+ (aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (QL_ADDG): New.
+ (aarch64_opcode_table): Add addg, subg, irg and gmi.
+ (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
+ * aarch64-asm.c (aarch64_ins_imm): Add case for
+ operand_need_shift_by_four.
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+
+2018-11-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_memtag): New.
+ (MEMTAG, MEMTAG_INSN): New.
+
+2018-11-06 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
+ with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
+
+2018-11-06 Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
+ (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
+ (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
+ (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
+ Don't return zero on error, insert mask bits instead.
+ (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
+ (insert_sh6, extract_sh6): Delete dead code.
+ (insert_sprbat, insert_sprg): Use unsigned comparisions.
+ (powerpc_operands <OIMM>): Set shift count rather than using
+ PPC_OPSHIFT_INV.
+ <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
+ vpbroadcast{d,q} with GPR operand.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
+ * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
+ cases up one level in the hierarchy.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
+ MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
+ (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
+ into MOD_VEX_0F93_P_3_LEN_0.
+ (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
+ operand cases up one level in the hierarchy.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
+ VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
+ EVEX_W_0F3A22_P_2): Delete.
+ (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
+ entries up one level in the hierarchy.
+ (OP_E_memory): Handle dq_mode when determining Disp8 shift
+ value.
+ * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
+ entries up one level in the hierarchy.
+ * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
+ VexWIG for AVX flavors.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
+ vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
+ vcvtusi2ss, kmovd): Drop VexW=1.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
+ EVex512, EVexLIG, EVexDYN): New.
+ (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
+ insns): Use Vex128 instead of Vex=3 (aka VexLIG).
+ (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
+ of EVex=4 (aka EVexLIG).
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
+ (vpmaxub): Re-order attributes on AVX512BW flavor.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
+ vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
+ Vex=1 on AVX / AVX2 flavors.
+ (vpmaxub): Re-order attributes on AVX512BW flavor.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (VexW0, VexW1): New.
+ (vphadd*, vphsub*): Use VexW0 on XOP variants.
+ * i386-tbl.h: Re-generate.
+
+2018-10-22 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-dis.c (decode_possible_symbol): Add fallback case.
+ (rel_15_7): Likewise.
+
+2018-10-19 Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
+ (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
+ (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
+
+2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
+ corresponding to AARCH64_OPND_QLF_S_4B qualifier.
+
+2018-10-10 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
+ Size64. Add Size.
+ * i386-opc.h (Size16, Size32, Size64): Delete.
+ (Size): New.
+ (SIZE16, SIZE32, SIZE64): Define.
+ (struct i386_opcode_modifier): Drop size16, size32, and size64.
+ Add size.
+ * i386-opc.tbl (Size16, Size32, Size64): Define.
+ * i386-tbl.h: Re-generate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Add
+ SSBS in the check for one-bit immediate.
+ (aarch64_sys_regs): New entry for SSBS.
+ (aarch64_sys_reg_supported_p): New check for above.
+ (aarch64_pstatefields): New entry for SSBS.
+ (aarch64_pstatefield_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for
+ scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
+ (aarch64_sys_reg_supported_p): New checks for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
+ (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
+ with the hint immediate.
+ * aarch64-opc.c (aarch64_hint_options): New entries for
+ c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
+ (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
+ while checking for HINT_OPD_F_NOPRINT flag.
+ * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
+ extract value.
+ * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
+ (aarch64_opcode_table): Add entry for BTI.
+ (AARCH64_OPERANDS): Add new description for BTI targets.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for
+ rndr and rndrrs.
+ (aarch64_sys_reg_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
+ (aarch64_sys_ins_reg_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
+ AARCH64_OPND_SYSREG_SR.
+ * aarch64-opc.c (aarch64_print_operand): Likewise.
+ (aarch64_sys_regs_sr): Define table.
+ (aarch64_sys_ins_reg_supported_p): Check for RCTX with
+ AARCH64_FEATURE_PREDRES.
+ * aarch64-tbl.h (aarch64_feature_predres): New.
+ (PREDRES, PREDRES_INSN): New.
+ (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
+ (AARCH64_OPERANDS): Add new description for SYSREG_SR.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_sb): New.
+ (SB, SB_INSN): New.
+ (aarch64_opcode_table): Add entry for sb.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
projects / deliverable / binutils-gdb.git / blobdiff