x86: adjust {,E}VEX.W handling outside of 64-bit mode

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 3d26869e51f6225131c1e899f1907b63d1f2ce8c..8b88018bd8f59473b72f0df9fab54d242a49410f 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,45 @@
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
+       vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
+       vcvtusi2ss, kmovd): Drop VexW=1.
+       * i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
+       EVex512, EVexLIG, EVexDYN): New.
+       (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
+       insns): Use Vex128 instead of Vex=3 (aka VexLIG).
+       (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
+       of EVex=4 (aka EVexLIG).
+       * i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
+       (vpmaxub): Re-order attributes on AVX512BW flavor.
+       * i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
+       vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
+       Vex=1 on AVX / AVX2 flavors.
+       (vpmaxub): Re-order attributes on AVX512BW flavor.
+       * i386-tbl.h: Re-generate.
+
+2018-11-06  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (VexW0, VexW1): New.
+       (vphadd*, vphsub*): Use VexW0 on XOP variants.
+       * i386-tbl.h: Re-generate.
+
+2018-10-22  John Darrington  <john@darrington.wattle.id.au>
+
+       * s12z-dis.c (decode_possible_symbol): Add fallback case.
+       (rel_15_7): Likewise.
+
 2018-10-19  Tamar Christina  <tamar.christina@arm.com>
 
        * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.