+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
+ vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
+ vcvtusi2ss, kmovd): Drop VexW=1.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
+ EVex512, EVexLIG, EVexDYN): New.
+ (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
+ insns): Use Vex128 instead of Vex=3 (aka VexLIG).
+ (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
+ of EVex=4 (aka EVexLIG).
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
+ (vpmaxub): Re-order attributes on AVX512BW flavor.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
+ vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
+ Vex=1 on AVX / AVX2 flavors.
+ (vpmaxub): Re-order attributes on AVX512BW flavor.
+ * i386-tbl.h: Re-generate.
+
+2018-11-06 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (VexW0, VexW1): New.
+ (vphadd*, vphsub*): Use VexW0 on XOP variants.
+ * i386-tbl.h: Re-generate.
+
+2018-10-22 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-dis.c (decode_possible_symbol): Add fallback case.
+ (rel_15_7): Likewise.
+
+2018-10-19 Tamar Christina <tamar.christina@arm.com>
+
+ * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
+ (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
+ (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
+
+2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
+ corresponding to AARCH64_OPND_QLF_S_4B qualifier.
+
+2018-10-10 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
+ Size64. Add Size.
+ * i386-opc.h (Size16, Size32, Size64): Delete.
+ (Size): New.
+ (SIZE16, SIZE32, SIZE64): Define.
+ (struct i386_opcode_modifier): Drop size16, size32, and size64.
+ Add size.
+ * i386-opc.tbl (Size16, Size32, Size64): Define.
+ * i386-tbl.h: Re-generate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (operand_general_constraint_met_p): Add
+ SSBS in the check for one-bit immediate.
+ (aarch64_sys_regs): New entry for SSBS.
+ (aarch64_sys_reg_supported_p): New check for above.
+ (aarch64_pstatefields): New entry for SSBS.
+ (aarch64_pstatefield_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for
+ scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
+ (aarch64_sys_reg_supported_p): New checks for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
+ (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
+ with the hint immediate.
+ * aarch64-opc.c (aarch64_hint_options): New entries for
+ c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
+ (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
+ while checking for HINT_OPD_F_NOPRINT flag.
+ * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
+ extract value.
+ * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
+ (aarch64_opcode_table): Add entry for BTI.
+ (AARCH64_OPERANDS): Add new description for BTI targets.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): New entries for
+ rndr and rndrrs.
+ (aarch64_sys_reg_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
+ (aarch64_sys_ins_reg_supported_p): New check for above.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
+ AARCH64_OPND_SYSREG_SR.
+ * aarch64-opc.c (aarch64_print_operand): Likewise.
+ (aarch64_sys_regs_sr): Define table.
+ (aarch64_sys_ins_reg_supported_p): Check for RCTX with
+ AARCH64_FEATURE_PREDRES.
+ * aarch64-tbl.h (aarch64_feature_predres): New.
+ (PREDRES, PREDRES_INSN): New.
+ (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
+ (AARCH64_OPERANDS): Add new description for SYSREG_SR.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-10-09 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_sb): New.
+ (SB, SB_INSN): New.
+ (aarch64_opcode_table): Add entry for sb.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_flagmanip): New.
projects / deliverable / binutils-gdb.git / blobdiff