x86: Add CheckRegSize to AVX512_BF16 instructions with Disp8ShiftVL

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index e6950acc17dede894b0366a8e882ad006aeb4a33..8c881a2c5869bcfccd30f44a2a31992401dcec32 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,80 @@
+2019-05-28  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/24625
+       * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
+       Disp8ShiftVL.
+       * i386-tbl.h: Regenerated.
+
+2019-05-24  Alan Modra  <amodra@gmail.com>
+
+       * po/POTFILES.in: Regenerate.
+
+2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
+           Alan Modra  <amodra@gmail.com>
+
+       * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
+       (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
+       (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
+       (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
+       XTOP>): Define and add entries.
+       (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
+       (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
+       pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
+       plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
+
+2019-05-24  Peter Bergner  <bergner@linux.ibm.com>
+           Alan Modra  <amodra@gmail.com>
+
+       * ppc-dis.c (ppc_opts): Add "future" entry.
+       (PREFIX_OPCD_SEGS): Define.
+       (prefix_opcd_indices): New array.
+       (disassemble_init_powerpc): Initialize prefix_opcd_indices.
+       (lookup_prefix): New function.
+       (print_insn_powerpc): Handle 64-bit prefix instructions.
+       * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
+       (PMRR, POWERXX): Define.
+       (prefix_opcodes): New instruction table.
+       (prefix_num_opcodes): New constant.
+
+2019-05-23  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
+       * configure: Regenerated.
+       * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
+       and cpu/bpf.opc.
+       (HFILES): Add bpf-desc.h and bpf-opc.h.
+       (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
+       bpf-ibld.c and bpf-opc.c.
+       (BPF_DEPS): Define.
+       * Makefile.in: Regenerated.
+       * disassemble.c (ARCH_bpf): Define.
+       (disassembler): Add case for bfd_arch_bpf.
+       (disassemble_init_for_target): Likewise.
+       (enum epbf_isa_attr): Define.
+       * disassemble.h: extern print_insn_bpf.
+       * bpf-asm.c: Generated.
+       * bpf-opc.h: Likewise.
+       * bpf-opc.c: Likewise.
+       * bpf-ibld.c: Likewise.
+       * bpf-dis.c: Likewise.
+       * bpf-desc.h: Likewise.
+       * bpf-desc.c: Likewise.
+
+2019-05-21  Sudakshina Das  <sudi.das@arm.com>
+
+       * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
+       and VMSR with the new operands.
+
+2019-05-21  Sudakshina Das  <sudi.das@arm.com>
+
+       * arm-dis.c (enum mve_instructions): New enum
+       for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
+       and cneg.
+       (mve_opcodes): New instructions as above.
+       (is_mve_encoding_conflict): Add cases for csinc, csinv,
+       csneg and csel.
+       (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
+
 2019-05-21  Sudakshina Das  <sudi.das@arm.com>
 
        * arm-dis.c (emun mve_instructions): Updated for new instructions.