+2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24625
+ * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
+ Disp8ShiftVL.
+ * i386-tbl.h: Regenerated.
+
+2019-05-24 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
+2019-05-24 Peter Bergner <bergner@linux.ibm.com>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
+ (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
+ (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
+ (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
+ XTOP>): Define and add entries.
+ (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
+ (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
+ pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
+ plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
+
+2019-05-24 Peter Bergner <bergner@linux.ibm.com>
+ Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (ppc_opts): Add "future" entry.
+ (PREFIX_OPCD_SEGS): Define.
+ (prefix_opcd_indices): New array.
+ (disassemble_init_powerpc): Initialize prefix_opcd_indices.
+ (lookup_prefix): New function.
+ (print_insn_powerpc): Handle 64-bit prefix instructions.
+ * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
+ (PMRR, POWERXX): Define.
+ (prefix_opcodes): New instruction table.
+ (prefix_num_opcodes): New constant.
+
+2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
+ * configure: Regenerated.
+ * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
+ and cpu/bpf.opc.
+ (HFILES): Add bpf-desc.h and bpf-opc.h.
+ (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
+ bpf-ibld.c and bpf-opc.c.
+ (BPF_DEPS): Define.
+ * Makefile.in: Regenerated.
+ * disassemble.c (ARCH_bpf): Define.
+ (disassembler): Add case for bfd_arch_bpf.
+ (disassemble_init_for_target): Likewise.
+ (enum epbf_isa_attr): Define.
+ * disassemble.h: extern print_insn_bpf.
+ * bpf-asm.c: Generated.
+ * bpf-opc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-ibld.c: Likewise.
+ * bpf-dis.c: Likewise.
+ * bpf-desc.h: Likewise.
+ * bpf-desc.c: Likewise.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
+ and VMSR with the new operands.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (enum mve_instructions): New enum
+ for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
+ and cneg.
+ (mve_opcodes): New instructions as above.
+ (is_mve_encoding_conflict): Add cases for csinc, csinv,
+ csneg and csel.
+ (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
+
+2019-05-21 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (emun mve_instructions): Updated for new instructions.
+ (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
+ sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
+ uqshl, urshrl and urshr.
+ (is_mve_okay_in_it): Add new instructions to TRUE list.
+ (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
+ (print_insn_mve): Updated to accept new %j,
+ %<bitfield>m and %<bitfield>n patterns.
+
+2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Change source register
+ constraint for DAUI.
+
+2019-05-20 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (enum mve_undefined): Add new reasons.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (enum mve_instructions): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): Add new instructions.
+ (print_insn_thumb32): Handle new instructions.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_undefined): Add new reasons.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_size): Likewise.
+ (print_mve_shift_n): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_rotate): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_undefined): Add new reasons.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new reasons.
+ (enum mve_undefined): Likewise.
+ (is_mve_okay_in_it): Handle new isntructions.
+ (is_mve_encoding_conflict): Likewise.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_vmov_index): Likewise.
+ (print_simd_imm8): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new reasons.
+ (enum mve_undefined): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_unpredictable): Likewise.
+ (print_mve_rounding_mode): Likewise.
+ (print_mve_vcvt_size): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new reasons.
+ (enum mve_undefined): Likewise.
+ (is_mve_undefined): Handle new instructions.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_unpredictable): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_undefined): Add new reasons.
+ (insns): Add new instructions.
+ (is_mve_encoding_conflict):
+ (print_mve_vld_str_addr): New print function.
+ (is_mve_undefined): Handle new instructions.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_size): Likewise.
+ (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
+ (print_insn_mve): Handle new operands.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new reasons.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_unpredictable): Likewise.
+ (mve_opcodes): Add new instructions.
+ (print_mve_unpredictable): Handle new reasons.
+ (print_mve_register_blocks): New print function.
+ (print_mve_size): Handle new instructions.
+ (print_insn_mve): Likewise.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new reasons.
+ (enum mve_undefined): Likewise.
+ (is_mve_encoding_conflict): Handle new instructions.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (coprocessor_opcodes): Move NEON VDUP from here...
+ (neon_opcodes): ... to here.
+ (mve_opcodes): Add new instructions.
+ (print_mve_undefined): Handle new reasons.
+ (print_mve_unpredictable): Likewise.
+ (print_mve_size): Handle new instructions.
+ (print_insn_neon): Handle vdup.
+ (print_insn_mve): Handle new operands.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): Add new instructions.
+ (enum mve_unpredictable): Add new values.
+ (mve_opcodes): Add new instructions.
+ (vec_condnames): New array with vector conditions.
+ (mve_predicatenames): New array with predicate suffixes.
+ (mve_vec_sizename): New array with vector sizes.
+ (enum vpt_pred_state): New enum with vector predication states.
+ (struct vpt_block): New struct type for vpt blocks.
+ (vpt_block_state): Global struct to keep track of state.
+ (mve_extract_pred_mask): New helper function.
+ (num_instructions_vpt_block): Likewise.
+ (mark_outside_vpt_block): Likewise.
+ (mark_inside_vpt_block): Likewise.
+ (invert_next_predicate_state): Likewise.
+ (update_next_predicate_state): Likewise.
+ (update_vpt_block_state): Likewise.
+ (is_vpt_instruction): Likewise.
+ (is_mve_encoding_conflict): Add entries for new instructions.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_unpredictable): Handle new cases.
+ (print_instruction_predicate): Likewise.
+ (print_mve_size): New function.
+ (print_vec_condition): New function.
+ (print_insn_mve): Handle vpt blocks and new print operands.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
+ 8, 14 and 15 for Armv8.1-M Mainline.
+
+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+ Michael Collison <michael.collison@arm.com>
+
+ * arm-dis.c (enum mve_instructions): New enum.
+ (enum mve_unpredictable): Likewise.
+ (enum mve_undefined): Likewise.
+ (struct mopcode32): New struct.
+ (is_mve_okay_in_it): New function.
+ (is_mve_architecture): Likewise.
+ (arm_decode_field): Likewise.
+ (arm_decode_field_multiple): Likewise.
+ (is_mve_encoding_conflict): Likewise.
+ (is_mve_undefined): Likewise.
+ (is_mve_unpredictable): Likewise.
+ (print_mve_undefined): Likewise.
+ (print_mve_unpredictable): Likewise.
+ (print_insn_coprocessor_1): Use arm_decode_field_multiple.
+ (print_insn_mve): New function.
+ (print_insn_thumb32): Handle MVE architecture.
+ (select_arm_features): Force thumb for Armv8.1-m Mainline.
+
+2019-05-10 Nick Clifton <nickc@redhat.com>
+
+ PR 24538
+ * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
+ end of the table prematurely.
+
+2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
+ macros for R6.
+
+2019-05-11 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
+ when -Mraw is in effect.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-tbl.h (OP_SVE_BBU): New variant set.
+ (OP_SVE_BBB): New variant set.
+ (OP_SVE_DDDD): New variant set.
+ (OP_SVE_HHH): New variant set.
+ (OP_SVE_HHHU): New variant set.
+ (OP_SVE_SSS): New variant set.
+ (OP_SVE_SSSU): New variant set.
+ (OP_SVE_SHH): New variant set.
+ (OP_SVE_SBBU): New variant set.
+ (OP_SVE_DSS): New variant set.
+ (OP_SVE_DHHU): New variant set.
+ (OP_SVE_VMV_HSD_BHS): New variant set.
+ (OP_SVE_VVU_HSD_BHS): New variant set.
+ (OP_SVE_VVVU_SD_BH): New variant set.
+ (OP_SVE_VVVU_BHSD): New variant set.
+ (OP_SVE_VVV_QHD_DBS): New variant set.
+ (OP_SVE_VVV_HSD_BHS): New variant set.
+ (OP_SVE_VVV_HSD_BHS2): New variant set.
+ (OP_SVE_VVV_BHS_HSD): New variant set.
+ (OP_SVE_VV_BHS_HSD): New variant set.
+ (OP_SVE_VVV_SD): New variant set.
+ (OP_SVE_VVU_BHS_HSD): New variant set.
+ (OP_SVE_VZVV_SD): New variant set.
+ (OP_SVE_VZVV_BH): New variant set.
+ (OP_SVE_VZV_SD): New variant set.
+ (aarch64_opcode_table): Add sve2 instructions.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_SHLIMM_UNPRED_22.
+ (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_size_tsz_bhs iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_size_tsz_bhs iclass decode.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_Zm4_11_INDEX.
+ (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
+ (fields): Handle SVE_i2h field.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_shift_tsz_bhsd iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_shift_tsz_bhsd iclass decode.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-asm.c (aarch64_ins_sve_shrimm):
+ (aarch64_encode_variant_using_iclass): Handle
+ sve_shift_tsz_hsd iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_shift_tsz_hsd iclass decode.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_SHRIMM_UNPRED_22.
+ (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
+ operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_size_013 iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_size_013 iclass decode.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_size_bh iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_size_bh iclass decode.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_size_sd2 iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_size_sd2 iclass decode.
+ * aarch64-opc.c (fields): Handle SVE_sz2 field.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_ADDR_ZX.
+ (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_Zm3_11_INDEX.
+ (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
+ (fields): Handle SVE_i3l and SVE_i3h2 fields.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
+ fields.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
+ sve_size_hsd2 iclass encode.
+ * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
+ sve_size_hsd2 iclass decode.
+ * aarch64-opc.c (fields): Handle SVE_size field.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
+ for SVE_IMM_ROT3.
+ (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
+ (fields): Handle SVE_rot3 field.
+ * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
+ * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
+ instructions.
+
+2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * aarch64-tbl.h
+ (aarch64_feature_sve2, aarch64_feature_sve2aes,
+ aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
+ aarch64_feature_sve2bitperm): New feature sets.
+ (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
+ for feature set addresses.
+ (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
+ SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
+
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): Add ISA
+ argument and set ASE_EVA_R6 appropriately.
+ (set_default_mips_dis_options): Pass ISA to above.
+ (parse_mips_dis_option): Likewise.
+ * mips-opc.c (EVAR6): New macro.
+ (mips_builtin_opcodes): Add llwpe, scwpe.
+
+2019-05-01 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-asm-2.c: Regenerated.
+ * aarch64-dis-2.c: Regenerated.
+ * aarch64-opc-2.c: Regenerated.
+ * aarch64-opc.c (operand_general_constraint_met_p): Add case for
+ AARCH64_OPND_TME_UIMM16.
+ (aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (QL_IMM_NIL): New.
+ (TME): New.
+ (_TME_INSN): New.
+ (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
+
+2019-04-29 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
+
+2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.h: Add extern "C" bracketing to help
+ users who wish to use this interface in c++ code.
+
+2019-04-24 John Darrington <john@darrington.wattle.id.au>
+
+ * s12z-opc.c (bm_decode): Handle bit map operations with the
+ "reserved0" mode.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
+ specifier. Add entries for VLDR and VSTR of system registers.
+ (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
+ coprocessor instructions on Armv8.1-M Mainline targets. Add handling
+ of %J and %K format specifier.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
+ Add new entries for VSCCLRM instruction.
+ (print_insn_coprocessor): Handle new %C format control code.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (enum isa): New enum.
+ (struct sopcode32): New structure.
+ (coprocessor_opcodes): change type of entries to struct sopcode32 and
+ set isa field of all current entries to ANY.
+ (print_insn_coprocessor): Change type of insn to struct sopcode32.
+ Only match an entry if its isa field allows the current mode.
+
+2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
+ CLRM.
+ (print_insn_thumb32): Add logic to print %n CLRM register list.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %P
+ and %Q patterns.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
+ (print_insn_thumb32): Edit the switch case for %Z.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): New instruction bfl.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
+ Arm register with r13 and r15 unpredictable.
+ (thumb32_opcodes): New instructions for bfx and bflx.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (thumb32_opcodes): New instructions for bf.
+
+2019-04-15 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
+
2019-04-15 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.