+2019-07-01 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
+ Delete.
+
+2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24719
+ * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
+ EVEX_LEN_0F38C7_R_6_P_2_W_1.
+ * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
+ PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
+ PREFIX_EVEX_0F38C6_REG_6 entries.
+ * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
+ EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
+ EVEX_W_0F38C7_R_6_P_2 entries.
+ * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
+ EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
+
+2019-06-27 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
+ VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
+ VEX_LEN_0F2D_P_3): Delete.
+ (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
+ vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
+ (prefix_table): ... here.
+
+2019-06-27 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Iq): Delete.
+ (Id): New.
+ (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
+ TBM insns.
+ (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
+ vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
+ (OP_E_memory): Also honor needindex when deciding whether an
+ address size prefix needs printing.
+ (OP_I): Remove handling of q_mode. Add handling of d_mode.
+
+2019-06-26 Jim Wilson <jimw@sifive.com>
+
+ PR binutils/24739
+ * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
+ Set info->display_endian to info->endian_code.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
+ entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
+ OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
+ OPERAND_TYPE_ACC64 entries.
+ * i386-init.h: Re-generate.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
+ Delete.
+ (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
+ of dqa_mode.
+ * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
+ entries here.
+ * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
+ entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
+ variables.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
+ Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
+ movnti.
+ * i386-opc.tbl (movnti): Add IgnoreSize.
+ * i386-tbl.h: Re-generate.
+
+2019-06-25 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (and): Mark Imm8S form for optimization.
+ * i386-tbl.h: Re-generate.
+
+2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis-evex.h: Break into ...
+ * i386-dis-evex-len.h: New file.
+ * i386-dis-evex-mod.h: Likewise.
+ * i386-dis-evex-prefix.h: Likewise.
+ * i386-dis-evex-reg.h: Likewise.
+ * i386-dis-evex-w.h: Likewise.
+ * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
+ i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
+ i386-dis-evex-mod.h.
+
+2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24700
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
+ EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
+ EVEX_W_0F385B_P_2.
+ (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
+ EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
+ EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
+ EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
+ EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
+ EVEX_LEN_0F385B_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
+ (EVEX_LEN_0F3819_P_2_W_1): Likewise.
+ (EVEX_LEN_0F381A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F381A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F381B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F381B_P_2_W_1): Likewise.
+ (EVEX_LEN_0F385A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F385A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F385B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F385B_P_2_W_1): Likewise.
+
+2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24691
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
+ EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
+ EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
+ (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
+ EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
+ EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
+ EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
+ EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
+ EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
+ EVEX_LEN_0F3A43_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
+ (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
+
+2019-06-14 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po; Updated French translation.
+
+2019-06-13 Stafford Horne <shorne@gmail.com>
+
+ * or1k-asm.c: Regenerated.
+ * or1k-desc.c: Regenerated.
+ * or1k-desc.h: Regenerated.
+ * or1k-dis.c: Regenerated.
+ * or1k-ibld.c: Regenerated.
+ * or1k-opc.c: Regenerated.
+ * or1k-opc.h: Regenerated.
+ * or1k-opinst.c: Regenerated.
+
+2019-06-12 Peter Bergner <bergner@linux.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
+
+2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24633
+ * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
+ EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
+ (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
+ EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
+ EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
+ EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
+ EVEX_LEN_0F3A1B_P_2_W_1.
+ * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
+ (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
+ (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
+ (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
+
+2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/24626
+ * i386-dis.c (print_insn): Check for unused VEX.vvvv and
+ EVEX.vvvv when disassembling VEX and EVEX instructions.
+ (OP_VEX): Set vex.register_specifier to 0 after readding
+ vex.register_specifier.
+ (OP_Vex_2src_1): Likewise.
+ (OP_Vex_2src_2): Likewise.
+ (OP_LWP_E): Likewise.
+ (OP_EX_Vex): Don't check vex.register_specifier.
+ (OP_XMM_Vex): Likewise.
+
+2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
+ * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
+ instructions.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
+ CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
+ (cpu_flags): Add CpuAVX512_VP2INTERSECT.
+ * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
+ (i386_cpu_flags): Add cpuavx512_vp2intersect.
+ * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
+ Lili Cui <lili.cui@intel.com>
+
+ * doc/c-i386.texi: Document enqcmd.
+ * testsuite/gas/i386/enqcmd-intel.d: New file.
+ * testsuite/gas/i386/enqcmd-inval.l: Likewise.
+ * testsuite/gas/i386/enqcmd-inval.s: Likewise.
+ * testsuite/gas/i386/enqcmd.d: Likewise.
+ * testsuite/gas/i386/enqcmd.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
+ * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
+ * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
+ enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
+ and x86-64-enqcmd.
+
+2019-06-04 Alan Hayward <alan.hayward@arm.com>
+
+ * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
+
+2019-06-03 Alan Modra <amodra@gmail.com>
+
+ * ppc-dis.c (prefix_opcd_indices): Correct size.
+
+2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/24625
+ * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
+ Disp8ShiftVL.
+ * i386-tbl.h: Regenerated.
+
+2019-05-24 Alan Modra <amodra@gmail.com>
+
+ * po/POTFILES.in: Regenerate.
+
2019-05-24 Peter Bergner <bergner@linux.ibm.com>
Alan Modra <amodra@gmail.com>
projects / deliverable / binutils-gdb.git / blobdiff