+2020-01-30 Alan Modra <amodra@gmail.com>
+
+ * m32c-ibld.c: Regenerate.
+
+2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * bpf-opc.c: Regenerate.
+
+2020-01-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
+ (dis386): Use them to replace C2/C3 table entries.
+ (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
+ * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
+ ones. Use Size64 instead of DefaultSize on Intel64 ones.
+ * i386-tbl.h: Re-generate.
+
+2020-01-30 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
+ forms.
+ (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
+ DefaultSize.
+ * i386-tbl.h: Re-generate.
+
+2020-01-30 Alan Modra <amodra@gmail.com>
+
+ * tic4x-dis.c (tic4x_dp): Make unsigned.
+
+2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
+ Jan Beulich <jbeulich@suse.com>
+
+ PR binutils/25445
+ * i386-dis.c (MOVSXD_Fixup): New function.
+ (movsxd_mode): New enum.
+ (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
+ (intel_operand_size): Handle movsxd_mode.
+ (OP_E_register): Likewise.
+ (OP_G): Likewise.
+ * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
+ register on movsxd. Add movsxd with 16-bit destination register
+ for AMD64 and Intel64 ISAs.
+ * i386-tbl.h: Regenerated.
+
+2020-01-27 Tamar Christina <tamar.christina@arm.com>
+
+ PR 25403
+ * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
+ * aarch64-asm-2.c: Regenerate
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2020-01-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (sysret): Drop DefaultSize.
+ * i386-tbl.h: Re-generate.
+
+2020-01-21 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
+ Dword.
+ (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
+ * i386-tbl.h: Re-generate.
+
+2020-01-20 Nick Clifton <nickc@redhat.com>
+
+ * po/de.po: Updated German translation.
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
+ * po/uk.po: Updated Ukranian translation.
+
+2020-01-20 Alan Modra <amodra@gmail.com>
+
+ * hppa-dis.c (fput_const): Remove useless cast.
+
+2020-01-20 Alan Modra <amodra@gmail.com>
+
+ * arm-dis.c (print_insn_arm): Wrap 'T' value.
+
+2020-01-18 Nick Clifton <nickc@redhat.com>
+
+ * configure: Regenerate.
+ * po/opcodes.pot: Regenerate.
+
+2020-01-18 Nick Clifton <nickc@redhat.com>
+
+ Binutils 2.34 branch created.
+
+2020-01-17 Christian Biesinger <cbiesinger@google.com>
+
+ * opintl.h: Fix spelling error (seperate).
+
+2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Add {vex} pseudo prefix.
+ * i386-tbl.h: Regenerated.
+
+2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ PR 25376
+ * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
+ (neon_opcodes): Likewise.
+ (select_arm_features): Make sure we enable MVE bits when selecting
+ armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
+ any architecture.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Drop stale comment from XOP section.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
+ (extractps): Add VexWIG to SSE2AVX forms.
+ * i386-tbl.h: Re-generate.
+
+2020-01-16 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
+ Size64 from and use VexW1 on SSE2AVX forms.
+ (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
+ VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
+ * i386-tbl.h: Re-generate.
+
+2020-01-15 Alan Modra <amodra@gmail.com>
+
+ * tic4x-dis.c (tic4x_version): Make unsigned long.
+ (optab, optab_special, registernames): New file scope vars.
+ (tic4x_print_register): Set up registernames rather than
+ malloc'd registertable.
+ (tic4x_disassemble): Delete optable and optable_special. Use
+ optab and optab_special instead. Throw away old optab,
+ optab_special and registernames when info->mach changes.
+
+2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25377
+ * z80-dis.c (suffix): Use .db instruction to generate double
+ prefix.
+
2020-01-14 Alan Modra <amodra@gmail.com>
* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short