x86: support VMGEXIT

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fc666d52052b1dcce3f9d073c09f6cd28722ac82..99958a10a5fadef7bca9b93ff0e1b4db5c690ad7 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,99 @@
+2020-03-04  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
+       (prefix_table): Move vmmcall here. Add vmgexit.
+       (rm_table): Replace vmmcall entry by prefix_table[] escape.
+       * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
+       (cpu_flags): Add CpuSEV_ES entry.
+       * i386-opc.h (CpuSEV_ES): New.
+       (union i386_cpu_flags): Add cpusev_es field.
+       * i386-opc.tbl (vmgexit): New.
+       * i386-init.h, i386-tbl.h: Re-generate.
+
+2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
+       with MnemonicSize.
+       * i386-opc.h (IGNORESIZE): New.
+       (DEFAULTSIZE): Likewise.
+       (IgnoreSize): Removed.
+       (DefaultSize): Likewise.
+       (MnemonicSize): New.
+       (i386_opcode_modifier): Replace ignoresize/defaultsize with
+       mnemonicsize.
+       * i386-opc.tbl (IgnoreSize): New.
+       (DefaultSize): Likewise.
+       * i386-tbl.h: Regenerated.
+
+2020-03-03  Sergey Belyashov  <sergey.belyashov@gmail.com>
+
+       PR 25627
+       * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
+       instructions.
+
+2020-03-03  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR gas/25622
+       * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
+       vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
+       * i386-tbl.h: Regenerated.
+
+2020-02-26  Alan Modra  <amodra@gmail.com>
+
+       * aarch64-asm.c: Indent labels correctly.
+       * aarch64-dis.c: Likewise.
+       * aarch64-gen.c: Likewise.
+       * aarch64-opc.c: Likewise.
+       * alpha-dis.c: Likewise.
+       * i386-dis.c: Likewise.
+       * nds32-asm.c: Likewise.
+       * nfp-dis.c: Likewise.
+       * visium-dis.c: Likewise.
+
+2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
+
+       * arc-regs.h (int_vector_base): Make it available for all ARC
+       CPUs.
+
+2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
+       changed.
+
+2020-02-19  Nelson Chu  <nelson.chu@sifive.com>
+
+       * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
+       c.mv/c.li if rs1 is zero.
+
+2020-02-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       * i386-gen.c (cpu_flag_init): Replace CpuABM with
+       CpuLZCNT|CpuPOPCNT.  Add CpuPOPCNT to CPU_SSE4_2_FLAGS.  Add
+       CPU_POPCNT_FLAGS.
+       (cpu_flags): Remove CpuABM.  Add CpuPOPCNT.
+       * i386-opc.h (CpuABM): Removed.
+       (CpuPOPCNT): New.
+       (i386_cpu_flags): Remove cpuabm.  Add cpupopcnt.
+       * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
+       popcnt.  Remove CpuABM from lzcnt.
+       * i386-init.h: Regenerated.
+       * i386-tbl.h: Likewise.
+
+2020-02-17  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
+       Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
+       VexW1 instead of open-coding them.
+       * i386-tbl.h: Re-generate.
+
+2020-02-17  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (AddrPrefixOpReg): Define.
+       (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
+       umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
+       templates. Drop NoRex64.
+       * i386-tbl.h: Re-generate.
+
 2020-02-17  Jan Beulich  <jbeulich@suse.com>
 
        PR gas/6518