+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
+ CPU_ANY_SSE4A_FLAGS.
+
+2020-02-17 Alan Modra <amodra@gmail.com>
+
+ * i386-gen.c (cpu_flag_init): Correct last change.
+
+2020-02-16 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
+ CPU_ANY_SSE4_FLAGS.
+
+2020-02-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl (movsx): Remove Intel syntax comments.
+ (movzx): Likewise.
+
+2020-02-14 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/25438
+ * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
+ destination for Cpu64-only variant.
+ (movzx): Fold patterns.
+ * i386-tbl.h: Re-generate.
+
+2020-02-13 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
+ CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
+ CPU_ANY_SSE4_FLAGS entry.
+ * i386-init.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
+ with Unspecified, making the present one AT&T syntax only.
+ * i386-tbl.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
+ * i386-tbl.h: Re-generate.
+
+2020-02-12 Jan Beulich <jbeulich@suse.com>
+
+ PR gas/24546
+ * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
+ * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
+ Amd64 and Intel64 templates.
+ (call, jmp): Likewise for far indirect variants. Dro
+ Unspecified.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
+ * i386-opc.h (ShortForm): Delete.
+ (struct i386_opcode_modifier): Remove shortform field.
+ * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
+ fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
+ fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
+ ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
+ Drop ShortForm.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
+ fucompi): Drop ShortForm from operand-less templates.
+ * i386-tbl.h: Re-generate.
+
+2020-02-11 Alan Modra <amodra@gmail.com>
+
+ * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
+ * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
+ * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
+ * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
+ * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
+
+2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (print_insn_cde): Define 'V' parse character.
+ (cde_opcodes): Add VCX* instructions.
+
+2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
+ Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * arm-dis.c (struct cdeopcode32): New.
+ (CDE_OPCODE): New macro.
+ (cde_opcodes): New disassembly table.
+ (regnames): New option to table.
+ (cde_coprocs): New global variable.
+ (print_insn_cde): New
+ (print_insn_thumb32): Use print_insn_cde.
+ (parse_arm_disassembler_options): Parse coprocN args.
+
+2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/25516
+ * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
+ with ISA64.
+ * i386-opc.h (AMD64): Removed.
+ (Intel64): Likewose.
+ (AMD64): New.
+ (INTEL64): Likewise.
+ (INTEL64ONLY): Likewise.
+ (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
+ * i386-opc.tbl (Amd64): New.
+ (Intel64): Likewise.
+ (Intel64Only): Likewise.
+ Replace AMD64 with Amd64. Update sysenter/sysenter with
+ Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
+ * i386-tbl.h: Regenerated.
+
+2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
+
+ PR 25469
+ * z80-dis.c: Add support for GBZ80 opcodes.
+
+2020-02-04 Alan Modra <amodra@gmail.com>
+
+ * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
+
2020-02-03 Alan Modra <amodra@gmail.com>
* m32c-ibld.c: Regenerate.