+2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h (vewt): Allow it for ARC EM family.
+
+2018-07-23 Alan Modra <amodra@gmail.com>
+
+ PR 23419
+ * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
+ opcode variants for mtspr/mfspr encodings.
+
+2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
+ Maciej W. Rozycki <macro@mips.com>
+
+ * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
+ loongson3a descriptors.
+ (parse_mips_ase_option): Handle -M loongson-mmi option.
+ (print_mips_disassembler_options): Document -M loongson-mmi.
+ * mips-opc.c (LMMI): New macro.
+ (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
+ instructions.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
+ vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
+ IgnoreSize and [XYZ]MMword where applicable.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
+ (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
+ (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
+ (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
+ AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
+ VPCLMULQDQ templates into their respective AVX512VL counterparts
+ where possible, using Disp8ShiftVL and CheckRegSize instead of
+ Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512DQ templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512BW templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl: Fold AVX512CD templates into their respective
+ AVX512VL counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h (DISP8_SHIFT_VL): New.
+ * i386-opc.tbl (Disp8ShiftVL): Define.
+ (various): Fold AVX512VL templates into their respective
+ AVX512F counterparts where possible, using Disp8ShiftVL and
+ CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
+ IgnoreSize) as appropriate.
+ * i386-tbl.h: Re-generate.
+
+2018-07-19 Jan Beulich <jbeulich@suse.com>
+
+ * Makefile.am: Change dependencies and rule for
+ $(srcdir)/i386-init.h.
+ * Makefile.in: Re-generate.
+ * i386-gen.c (process_i386_opcodes): New local variable
+ "marker". Drop opening of input file. Recognize marker and line
+ number directives.
+ * i386-opc.tbl (OPCODE_I386_H): Define.
+ (i386-opc.h): Include it.
+ (None): Undefine.
+
+2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/23418
+ * i386-opc.h (Byte): Update comments.
+ (Word): Likewise.
+ (Dword): Likewise.
+ (Fword): Likewise.
+ (Qword): Likewise.
+ (Tbyte): Likewise.
+ (Xmmword): Likewise.
+ (Ymmword): Likewise.
+ (Zmmword): Likewise.
+ * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
+ vcvttps2uqq.
+ * i386-tbl.h: Regenerated.
+
+2018-07-12 Sudakshina Das <sudi.das@arm.com>
+
+ * aarch64-tbl.h (aarch64_opcode_table): Add entry for
+ ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2018-07-12 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23192
+ * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
+ mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
+ umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
+ sqdmulh, sqrdmulh): Use Em16.
+
+2018-07-11 Sudakshina Das <sudi.das@arm.com>
+
+ * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
+ csdb together with them.
+ (thumb32_opcodes): Likewise.
+
+2018-07-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (monitor, monitorx): Add 64-bit template
+ requiring 32-bit registers as operands 2 and 3. Improve
+ comments.
+ (mwait, mwaitx): Fold templates. Improve comments.
+ OPERAND_TYPE_INOUTPORTREG.
+ * i386-tbl.h: Re-generate.
+
+2018-07-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-gen.c (operand_type_init): Remove
+ OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
+ OPERAND_TYPE_INOUTPORTREG.
+ * i386-init.h: Re-generate.
+
+2018-07-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.tbl (wrssd, wrussd): Add Dword.
+ (wrssq, wrussq): Add Qword.
+ * i386-tbl.h: Re-generate.
+
+2018-07-11 Jan Beulich <jbeulich@suse.com>
+
+ * i386-opc.h: Rename OTMax to OTNum.
+ (OTNumOfUints): Adjust calculation.
+ (OTUnused): Directly alias to OTNum.
+
+2018-07-09 Maciej W. Rozycki <macro@mips.com>
+
+ * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
+ `reg_xys'.
+ (lea_reg_xys): Likewise.
+ (print_insn_loop_primitive): Rename `reg' local variable to
+ `reg_dxy'.
+
+2018-07-06 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23242
+ * aarch64-tbl.h (ldarh): Fix disassembly mask.
+
+2018-07-06 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23369
+ * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
+ vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
+
+2018-07-02 Maciej W. Rozycki <macro@mips.com>
+
+ PR tdep/8282
+ * mips-dis.c (mips_option_arg_t): New enumeration.
+ (mips_options): New variable.
+ (disassembler_options_mips): New function.
+ (print_mips_disassembler_options): Reimplement in terms of
+ `disassembler_options_mips'.
+ * arm-dis.c (disassembler_options_arm): Adapt to using the
+ `disasm_options_and_args_t' structure.
+ * ppc-dis.c (disassembler_options_powerpc): Likewise.
+ * s390-dis.c (disassembler_options_s390): Likewise.
+
+2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
+ expected result.
+ * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
+ * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
+ * testsuite/ld-arm/tls-longplt.d: Likewise.
+
+2018-06-29 Tamar Christina <tamar.christina@arm.com>
+
+ PR binutils/23192
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+ * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
+ * aarch64-opc.c (operand_general_constraint_met_p,
+ aarch64_print_operand): Likewise.
+ * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
+ smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
+ fmlal2, fmlsl2.
+ (AARCH64_OPERANDS): Add Em2.
+
+2018-06-26 Nick Clifton <nickc@redhat.com>
+
+ * po/uk.po: Updated Ukranian translation.
+ * po/de.po: Updated German translation.
+ * po/pt_BR.po: Updated Brazilian Portuguese translation.
+
2018-06-26 Nick Clifton <nickc@redhat.com>
* nfp-dis.c: Fix spelling mistake.
projects / deliverable / binutils-gdb.git / blobdiff