+2005-09-30 Catherine Moore <clm@cm00re.com>
+
+ * Makefile.am: Bfin support.
+ * Makefile.in: Regenerated.
+ * aclocal.m4: Regenerated.
+ * bfin-dis.c: New file.
+ * configure.in: Bfin support.
+ * configure: Regenerated.
+ * disassemble.c (ARCH_bfin): Define.
+ (disassembler): Add case for bfd_arch_bfin.
+
+2005-09-28 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (stack_v_mode): Renamed from branch_v_mode.
+ (indirEv): Use it.
+ (stackEv): New.
+ (Ob64, Ov64): Rename to Ob, Ov. Delete unused original definitions.
+ (dis386): Document and use new 'V' meta character. Use it for
+ single-byte push/pop opcode forms. Use stackEv for mod-r/m push/pop
+ opcode forms. Correct typo in 'pop ss'. Replace Ob64/Ov64 by Ob/Ov.
+ (putop): 'q' suffix for 'T' and 'U' meta depends on DFLAG. Mark
+ data prefix as used whenever DFLAG was examined. Handle 'V'.
+ (intel_operand_size): Use stack_v_mode.
+ (OP_E): Use stack_v_mode, but handle only the special case of
+ 64-bit mode without operand size override here; fall through to
+ v_mode case otherwise.
+ (OP_REG): Special case rAX_reg ... rDI_reg only when 64-bit mode
+ and no operand size override is present.
+ (OP_J): Use get32s for obtaining the displacement also when rex64
+ is present.
+
+2005-09-08 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
+
+2005-09-06 Chao-ying Fu <fu@mips.com>
+
+ * mips-opc.c (MT32): New define.
+ (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
+ bottom to avoid opcode collision with "mftr" and "mttr".
+ Add MT instructions.
+ * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
+ (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
+ formats.
+
+2005-09-02 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add null terminator.
+
+2005-09-02 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (coprocessor_opcodes): New.
+ (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
+ (print_insn_coprocessor): New function.
+ (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
+ format characters.
+ (print_insn_thumb32): Use print_insn_coprocessor.
+
+2005-08-30 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
+
+2005-08-26 Jan Beulich <jbeulich@novell.com>
+
+ * i386-dis.c (intel_operand_size): New, broken out from OP_E for
+ re-use.
+ (OP_E): Call intel_operand_size, move call site out of mode
+ dependent code.
+ (OP_OFF): Call intel_operand_size if suffix_always. Remove
+ ATTRIBUTE_UNUSED from parameters.
+ (OP_OFF64): Likewise.
+ (OP_ESreg): Call intel_operand_size.
+ (OP_DSreg): Likewise.
+ (OP_DIR): Use colon rather than semicolon as separator of far
+ jump/call operands.
+
+2005-08-25 Chao-ying Fu <fu@mips.com>
+
+ * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
+ (mips_builtin_opcodes): Add DSP instructions.
+ * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
+ mips64, mips64r2.
+ (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
+ operand formats.
+
+2005-08-23 David Ung <davidu@mips.com>
+
+ * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
+ instructions to the table.
+
+2005-08-18 Alan Modra <amodra@bigpond.net.au>
+
+ * a29k-dis.c: Delete.
+ * Makefile.am: Remove a29k support.
+ * configure.in: Likewise.
+ * disassemble.c: Likewise.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
+
+ * ppc-dis.c (powerpc_dialect): Handle e300.
+ (print_ppc_disassembler_options): Likewise.
+ * ppc-opc.c (PPCE300): Define.
+ (powerpc_opcodes): Mark icbt as available for the e300.
+
+2005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
+
+ * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
+ Use "rp" instead of "%r2" in "b,l" insns.
+
+2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
+
+ * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
+ * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
+ (main): Likewise.
+ * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
+ and 4 bit optional masks.
+ (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
+ INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
+ (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
+ MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
+ (s390_opformats): Likewise.
+ * s390-opc.txt: Add new instructions for cpu type z9-109.
+
+2005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
+
+ * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
+
+2005-07-29 Paul Brook <paul@codesourcery.com>
+
+ * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
+
2005-07-29 Paul Brook <paul@codesourcery.com>
* arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
projects / deliverable / binutils-gdb.git / blobdiff