cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions

[deliverable/binutils-gdb.git] / opcodes / ChangeLog

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 314ef7f9e4ee38a232553fda6deef98ba6fda467..e1de65b5d4d6b582c7a369a41785d4846a84b83e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,52 @@
+2019-07-14  Jose E. Marchesi  <jose.marchesi@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-opc.c: Likewise.
+
+2019-07-10  Hans-Peter Nilsson  <hp@bitrange.com>
+
+       * arm-dis.c (print_insn_coprocessor): Rename index to
+       index_operand.
+
+2019-07-05  Kito Cheng <kito.cheng@sifive.com>
+
+       * riscv-opc.c (riscv_insn_types): Add r4 type.
+
+       * riscv-opc.c (riscv_insn_types): Add b and j type.
+
+       * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
+       format for sb type and correct s type.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
+       SVE FMOV alias of FCPY.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
+       to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
+
+2019-07-02  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
+       registers in an instruction prefixed by MOVPRFX.
+
+2019-07-01  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
+       sve_size_13 icode to account for variant behaviour of
+       pmull{t,b}.
+       * aarch64-dis-2.c: Regenerate.
+       * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
+       sve_size_13 icode to account for variant behaviour of
+       pmull{t,b}.
+       * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
+       (OP_SVE_VVV_Q_D): Add new qualifier.
+       (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
+       (struct aarch64_opcode): Split pmull{t,b} into those requiring
+       AES and those not.
+
 2019-07-01  Jan Beulich  <jbeulich@suse.com>
 
        * opcodes/i386-gen.c (operand_type_init): Remove