+2016-12-14 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Update comments on MIPS16e
+ compact jumps.
+
+2016-12-13 Renlin Li <renlin.li@arm.com>
+
+ * aarch64-opc.c (aarch64_opnd_qualifiers): New CR value range
+ qualifier.
+ (operand_general_constraint_met_p): Remove case for CP_REG.
+ (aarch64_print_operand): Print CRn, CRm operand using imm field.
+ * aarch64-tbl.h (QL_SYS): Use CR qualifier.
+ (QL_SYSL): Likewise.
+ (aarch64_opcode_table): Change CRn, CRm operand class and type.
+ * aarch64-opc-2.c : Regenerate.
+ * aarch64-asm-2.c : Likewise.
+ * aarch64-dis-2.c : Likewise.
+
+2016-12-12 Yao Qi <yao.qi@linaro.org>
+
+ * rx-dis.c: Include <setjmp.h>
+ (struct private): New.
+ (rx_get_byte): Check return value of read_memory_func, and
+ call memory_error_func and OPCODES_SIGLONGJMP on error.
+ (print_insn_rx): Call OPCODES_SIGSETJMP.
+
+2016-12-12 Yao Qi <yao.qi@linaro.org>
+
+ * rl78-dis.c: Include <setjmp.h>.
+ (struct private): New.
+ (rl78_get_byte): Check return value of read_memory_func, and
+ call memory_error_func and OPCODES_SIGLONGJMP on error.
+ (print_insn_rl78_common): Call OPCODES_SIGJMP.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'>'>: Remove cases.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (decode_mips16_operand) <'e'>: Use HINT rather
+ than UINT.
+
+2016-12-09 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_insn_mips16): Use a tab rather than a space
+ to separate `extend' and its uninterpreted argument output.
+ Separate hexadecimal halves of undecoded extended instructions
+ output.
+
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Remove extraneous
+ indentation space across.
+
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
+ adjustment for PC-relative operations following MIPS16e compact
+ jumps or undefined RR/J(AL)R(C) encodings.
+
+2016-12-08 Maciej W. Rozycki <macro@imgtec.com>
+
+ * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
+ variable to `reglane_index'.
+
+2016-12-08 Luis Machado <lgustavo@codesourcery.com>
+
+ * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
+
+2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
+
+2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips16-opc.c (mips16_opcodes): Update comment naming structure
+ members.
+
+2016-12-07 Maciej W. Rozycki <macro@imgtec.com>
+
+ * mips-dis.c (print_mips_disassembler_options): Reformat output.
+
+2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
+ (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
+
+2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * arm-dis.c (coprocessor_opcodes): Add vjcvt.
+
+2016-12-01 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/20893
+ * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
+ opcode designator.
+
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-opc.c (insert_ra_chk): New function.
+ (insert_rb_chk): Likewise.
+ (insert_rad): Update text error message.
+ (insert_rcd): Likewise.
+ (insert_rhv2): Likewise.
+ (insert_r0): Likewise.
+ (insert_r1): Likewise.
+ (insert_r2): Likewise.
+ (insert_r3): Likewise.
+ (insert_sp): Likewise.
+ (insert_gp): Likewise.
+ (insert_pcl): Likewise.
+ (insert_blink): Likewise.
+ (insert_ilink1): Likewise.
+ (insert_ilink2): Likewise.
+ (insert_ras): Likewise.
+ (insert_rbs): Likewise.
+ (insert_rcs): Likewise.
+ (insert_simm3s): Likewise.
+ (insert_rrange): Likewise.
+ (insert_fpel): Likewise.
+ (insert_blinkel): Likewise.
+ (insert_pcel): Likewise.
+ (insert_nps_3bit_dst): Likewise.
+ (insert_nps_3bit_dst_short): Likewise.
+ (insert_nps_3bit_src2_short): Likewise.
+ (insert_nps_bitop_size_2b): Likewise.
+ (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
+ (RA_CHK): Define.
+ (RB): Adjust.
+ (RB_CHK): Define.
+ (RC): Adjust.
+ * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
+ * arc-tbl.h (div, divu): All instructions are DIVREM class.
+ Change first insn argument to check for LP_COUNT usage.
+ (rem): Likewise.
+ (ld, ldd): All instructions are LOAD class. Change first insn
+ argument to check for LP_COUNT usage.
+ (st, std): All instructions are STORE class.
+ (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
+ Change first insn argument to check for LP_COUNT usage.
+ (mov): All instructions are MOVE class. Change first insn
+ argument to check for LP_COUNT usage.
+
+2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (is_compatible_p): Remove function.
+ (skip_this_opcode): Don't add any decoding class to decode list.
+ Remove warning.
+ (find_format_from_table): Go through all opcodes, and warn if we
+ use a guessed mnemonic.
+
+2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
+ Amit Pawar <amit.pawar@amd.com>
+
+ PR binutils/20637
+ * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
+ instructions.
+
+2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
+
+ * configure: Regenerate.
+
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (HWS_V8): Definition moved from
+ gas/config/tc-sparc.c.
+ (HWS_V9): Likewise.
+ (HWS_VA): Likewise.
+ (HWS_VB): Likewise.
+ (HWS_VC): Likewise.
+ (HWS_VD): Likewise.
+ (HWS_VE): Likewise.
+ (HWS_VV): Likewise.
+ (HWS_VM): Likewise.
+ (HWS2_VM): Likewise.
+ (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
+ existing entries.
+
+2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
+ instructions.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
+ (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
+ (aarch64_opcode_table): Add fcmla and fcadd.
+ (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
+ * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
+ * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
+ * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
+ * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
+ * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
+ * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
+ (operand_general_constraint_met_p): Rotate and index range check.
+ (aarch64_print_operand): Handle rotate operand.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Likewise.
+ * aarch64-opc-2.c: Likewise.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
+ (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (QL_X1NIL): New.
+ (arch64_opcode_table): Add ldraa, ldrab.
+ (AARCH64_OPERANDS): Add "ADDR_SIMM10".
+ * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
+ * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
+ * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
+ * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
+ * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
+ * aarch64-opc.c (fields): Add data for FLD_S_simm10.
+ (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
+ (aarch64_print_operand): Likewise.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
+ brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (arch64_opcode_table): Add pacga.
+ (AARCH64_OPERANDS): Add Rm_SP.
+ * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
+ autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
+ autdzb, xpaci, xpacd.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
+ apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
+ apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
+ (aarch64_sys_reg_supported_p): Add feature test for new registers.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
+ (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
+ autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
+ autibsp.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+
+2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
+
+ * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20799
+ * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
+ * i386-dis.c (EdqwS): Removed.
+ (dqw_swap_mode): Likewise.
+ (intel_operand_size): Don't check dqw_swap_mode.
+ (OP_E_register): Likewise.
+ (OP_E_memory): Likewise.
+ (OP_G): Likewise.
+ (OP_EX): Likewise.
+ * i386-opc.tbl: Remove "S" from EVEX vpextrw.
+ * i386-tbl.h: Regerated.
+
+2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-opc.tbl: Merge AVX512F vmovq.
+ * i386-tbl.h: Regerated.
+
+2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20701
+ * i386-dis.c (THREE_BYTE_0F7A): Removed.
+ (dis386_twobyte): Don't use THREE_BYTE_0F7A.
+ (three_byte_table): Remove THREE_BYTE_0F7A.
+
+2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20775
+ * i386-dis.c (FGRPd9_2): Replace 0 with 1.
+ (FGRPd9_4): Replace 1 with 2.
+ (FGRPd9_5): Replace 2 with 3.
+ (FGRPd9_6): Replace 3 with 4.
+ (FGRPd9_7): Replace 4 with 5.
+ (FGRPda_5): Replace 5 with 6.
+ (FGRPdb_4): Replace 6 with 7.
+ (FGRPde_3): Replace 7 with 8.
+ (FGRPdf_4): Replace 8 with 9.
+ (fgrps): Add an entry for Bad_Opcode.
+
+2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-opc.c (arc_flag_operands): Add F_DI14.
+ (arc_flag_classes): Add C_DI14.
+ * arc-nps400-tbl.h: Add new exc instructions.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-dis.c (arc_insn_length): Return length 8 for instructions with
+ major opcode 0xa.
+ * arc-nps-400-tbl.h: Add dcmac instruction.
+ * arc-opc.c (arc_operands): Added operands for dcmac instruction.
+ (insert_nps_rbdouble_64): Added.
+ (extract_nps_rbdouble_64): Added.
+ (insert_nps_proto_size): Added.
+ (extract_nps_proto_size): Added.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-dis.c (struct arc_operand_iterator): Remove all fields
+ relating to long instruction processing, add new limm field.
+ (OPCODE): Rename to...
+ (OPCODE_32BIT_INSN): ...this.
+ (OPCODE_AC): Delete.
+ (skip_this_opcode): Handle different instruction lengths, update
+ macro name.
+ (special_flag_p): Update parameter type.
+ (find_format_from_table): Update for more instruction lengths.
+ (find_format_long_instructions): Delete.
+ (find_format): Update for more instruction lengths.
+ (arc_insn_length): Likewise.
+ (extract_operand_value): Update for more instruction lengths.
+ (operand_iterator_next): Remove code relating to long
+ instructions.
+ (arc_opcode_to_insn_type): New function.
+ (print_insn_arc):Update for more instructions lengths.
+ * arc-ext.c (extInstruction_t): Change argument type.
+ * arc-ext.h (extInstruction_t): Change argument type.
+ * arc-fxi.h: Change type unsigned to unsigned long long
+ extensively throughout.
+ * arc-nps400-tbl.h: Add long instructions taken from
+ arc_long_opcodes table in arc-opc.c.
+ * arc-opc.c: Update parameter types on insert/extract handlers.
+ (arc_long_opcodes): Delete.
+ (arc_num_long_opcodes): Delete.
+ (arc_opcode_len): Update for more instruction lengths.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
+
+2016-11-03 Graham Markall <graham.markall@embecosm.com>
+
+ * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
+ with arc_opcode_len.
+ (find_format_long_instructions): Likewise.
+ * arc-opc.c (arc_opcode_len): New function.
+
+2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * arc-nps400-tbl.h: Fix some instruction masks.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_82): Removed.
+ (X86_64_82_REG_0): Likewise.
+ (X86_64_82_REG_1): Likewise.
+ (X86_64_82_REG_2): Likewise.
+ (X86_64_82_REG_3): Likewise.
+ (X86_64_82_REG_4): Likewise.
+ (X86_64_82_REG_5): Likewise.
+ (X86_64_82_REG_6): Likewise.
+ (X86_64_82_REG_7): Likewise.
+ (X86_64_82): New.
+ (dis386): Use X86_64_82 instead of REG_82.
+ (reg_table): Remove REG_82.
+ (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
+ X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
+ X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
+ X86_64_82_REG_7.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/20754
+ * i386-dis.c (REG_82): New.
+ (X86_64_82_REG_0): Likewise.
+ (X86_64_82_REG_1): Likewise.
+ (X86_64_82_REG_2): Likewise.
+ (X86_64_82_REG_3): Likewise.
+ (X86_64_82_REG_4): Likewise.
+ (X86_64_82_REG_5): Likewise.
+ (X86_64_82_REG_6): Likewise.
+ (X86_64_82_REG_7): Likewise.
+ (dis386): Use REG_82.
+ (reg_table): Add REG_82.
+ (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
+ X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
+ X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
+
+2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (REG_82): Renamed to ...
+ (REG_83): This.
+ (dis386): Updated.
+ (reg_table): Likewise.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
+ CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4VNNIW.
+ * i386-opc.h (enum): (AVX512_4VNNIW): New.
+ (i386_cpu_flags): Add cpuavx512_4vnniw.
+ * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
+
+ * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
+ PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
+ * i386-dis-evex.h (evex_table): Updated.
+ * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
+ CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+ (cpu_flags): Add CpuAVX512_4FMAPS.
+ (opcode_modifiers): Add ImplicitQuadGroup modifier.
+ * i386-opc.h (AVX512_4FMAP): New.
+ (i386_cpu_flags): Add cpuavx512_4fmaps.
+ (ImplicitQuadGroup): New.
+ (i386_opcode_modifier): Add implicitquadgroup.
+ * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
+ * i386-init.h: Regenerate.
+ * i386-tbl.h: Ditto.
+
+2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ Add support for RISC-V architecture.
+ * configure.ac: Add entry for bfd_riscv_arch.
+ * configure: Regenerate.
+ * disassemble.c (disassembler): Add support for riscv.
+ (disassembler_usage): Likewise.
+ * riscv-dis.c: New file.
+ * riscv-opc.c: New file.
+
+2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
+ (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
+ (rm_table): Update the RM_0FAE_REG_7 entry.
+ * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
+ (cpu_flags): Remove CpuPCOMMIT.
+ * i386-opc.h (CpuPCOMMIT): Removed.
+ (i386_cpu_flags): Remove cpupcommit.
+ * i386-opc.tbl: Remove pcommit.
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20705
+ * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
+ the highest bit in VEX.vvvv for the 3-byte VEX prefix in
+ 32-bit mode. Don't check vex.register_specifier in 32-bit
+ mode.
+ (OP_VEX): Check for invalid mask registers.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20699
+ * i386-dis.c (OP_E_memory): Check addr32flag in stead of
+ sizeflag.
+
+2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/20704
+ * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
+
+2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
+
+ * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
+ local variable to `index_regno'.
+
+2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-tbl.h: Removed any "inv.+" instructions from the table.
+
+2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
+ usage on ISA basis.
+
+2016-10-11 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20666
+ * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
+
+2016-10-07 Jiong Wang <jiong.wang@arm.com>
+
+ PR target/20667
+ * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
+ available.
+
+2016-10-07 Alan Modra <amodra@gmail.com>
+
+ * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * aarch64-opc.c: Spell fall through comments consistently.
+ * i386-dis.c: Likewise.
+ * aarch64-dis.c: Add missing fall through comments.
+ * aarch64-opc.c: Likewise.
+ * arc-dis.c: Likewise.
+ * arm-dis.c: Likewise.
+ * i386-dis.c: Likewise.
+ * m68k-dis.c: Likewise.
+ * mep-asm.c: Likewise.
+ * ns32k-dis.c: Likewise.
+ * sh-dis.c: Likewise.
+ * tic4x-dis.c: Likewise.
+ * tic6x-dis.c: Likewise.
+ * vax-dis.c: Likewise.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * arc-ext.c (create_map): Add missing break.
+ * msp430-decode.opc (encode_as): Likewise.
+ * msp430-decode.c: Regenerate.
+
+2016-10-06 Alan Modra <amodra@gmail.com>
+
+ * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
+ * crx-dis.c (print_insn_crx): Likewise.
+
2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/20657