+2011-08-22 Nick Clifton <nickc@redhat.com>
+
+ * Makefile.am (CPUDIR): Redfine to point to top level cpu
+ directory.
+ (stamp-frv): Use CPUDIR.
+ (stamp-iq2000): Likewise.
+ (stamp-lm32): Likewise.
+ (stamp-m32c): Likewise.
+ (stamp-mt): Likewise.
+ (stamp-xc16x): Likewise.
+ * Makefile.in: Regenerate.
+
+2011-08-09 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
+ and "mips64r2".
+ (print_insn_args, print_insn_micromips): Handle MCU.
+ * micromips-opc.c (MC): New macro.
+ (micromips_opcodes): Add "aclr", "aset" and "iret".
+ * mips-opc.c (MC): New macro.
+ (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
+
+2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
+ (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
+ (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
+ (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
+ (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
+ (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
+ (WR_s): Update macro.
+ (micromips_opcodes): Update register use flags of: "addiu",
+ "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
+ "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
+ "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
+ "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
+ "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
+ "swm" and "xor" instructions.
+
+2011-08-05 David S. Miller <davem@davemloft.net>
+
+ * sparc-dis.c (v9a_ast_reg_names): Add "cps".
+ (X_RS3): New macro.
+ (print_insn_sparc): Handle '4', '5', and '(' format codes.
+ Accept %asr numbers below 28.
+ * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
+ instructions.
+
+2011-08-02 Quentin Neill <quentin.neill@amd.com>
+
+ * i386-dis.c (xop_table): Remove spurious bextr insn.
+
+2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR ld/13048
+ * i386-dis.c (print_insn): Optimize info->mach check.
+
+2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/13046
+ * i386-opc.tbl: Add Disp32S to 64bit call.
+ * i386-tbl.h: Regenerated.
+
+2011-07-24 Chao-ying Fu <fu@mips.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+
+ * micromips-opc.c: New file.
+ * mips-dis.c (micromips_to_32_reg_b_map): New array.
+ (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
+ (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
+ (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
+ (micromips_to_32_reg_q_map): Likewise.
+ (micromips_imm_b_map, micromips_imm_c_map): Likewise.
+ (micromips_ase): New variable.
+ (is_micromips): New function.
+ (set_default_mips_dis_options): Handle microMIPS ASE.
+ (print_insn_micromips): New function.
+ (is_compressed_mode_p): Likewise.
+ (_print_insn_mips): Handle microMIPS instructions.
+ * Makefile.am (CFILES): Add micromips-opc.c.
+ * configure.in (bfd_mips_arch): Add micromips-opc.lo.
+ * Makefile.in: Regenerate.
+ * configure: Regenerate.
+
+ * mips-dis.c (micromips_to_32_reg_h_map): New variable.
+ (micromips_to_32_reg_i_map): Likewise.
+ (micromips_to_32_reg_m_map): Likewise.
+ (micromips_to_32_reg_n_map): New macro.
+
+2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips-opc.c (NODS): New macro.
+ (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
+ (DSP_VOLA): Likewise.
+ (mips_builtin_opcodes): Add NODS annotation to "deret" and
+ "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
+ place of TRAP for "wait", "waiti" and "yield".
+ * mips16-opc.c (NODS): New macro.
+ (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
+ (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
+ "restore" and "save".
+
+2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.in: Handle bfd_k1om_arch.
+ * configure: Regenerated.
+
+ * disassemble.c (disassembler): Handle bfd_k1om_arch.
+
+ * i386-dis.c (print_insn): Handle bfd_mach_k1om and
+ bfd_mach_k1om_intel_syntax.
+
+ * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
+ ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
+ (cpu_flags): Add CpuK1OM.
+
+ * i386-opc.h (CpuK1OM): New.
+ (i386_cpu_flags): Add cpuk1om.
+
+ * i386-init.h: Regenerated.
+ * i386-tbl.h: Likewise.
+
+2011-07-12 Nick Clifton <nickc@redhat.com>
+
+ * arm-dis.c (print_insn_arm): Revert previous, undocumented,
+ accidental change.
+
+2011-07-01 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/12329
+ * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
+ insns using post-increment addressing.
+
+2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (vex_len_table): Update rorxS.
+
+2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ AVX Programming Reference (June, 2011)
+ * i386-dis.c (vex_len_table): Correct rorxS.
+
+ * i386-opc.tbl: Correct rorx.
+ * i386-tbl.h: Regenerated.
+
+2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ * tilegx-opc.c (find_opcode): Replace "index" with "i".
+ * tilepro-opc.c (find_opcode): Likewise.
+
+2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips16-opc.c (jalrc, jrc): Move earlier in file.
+
+2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
+
+ * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
+ PREFIX_VEX_0F388E.
+
+2011-06-17 Andreas Schwab <schwab@redhat.com>
+
+ * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
+ (MOSTLYCLEANFILES): ... here.
+ * Makefile.in: Regenerate.
+
+2011-06-14 Alan Modra <amodra@gmail.com>
+
+ * Makefile.in: Regenerate.
+
2011-06-13 Walter Lee <walt@tilera.com>
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
2011-02-09 Michael Snyder <msnyder@vmware.com>
- * i386-dis.c (OP_J): Parenthesize expression to prevent
+ * i386-dis.c (OP_J): Parenthesize expression to prevent
truncated addresses.
(print_insn): Fix indentation off-by-one.
projects / deliverable / binutils-gdb.git / blobdiff