x86: Don't disable SSE3 when disabling SSE4a

[deliverable/binutils-gdb.git] / opcodes / aarch64-asm.c

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 6be17f9246ecab85c18ce5eb9ac1a4b10d5d6527..36f84e800ed5e12bfc62ee005e4ffe317a49dac4 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1,5 +1,5 @@
 /* aarch64-asm.c -- AArch64 assembler support.
-   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -130,6 +130,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:
+       case AARCH64_OPND_QLF_S_2H:
          /* L:H */
          assert (reglane_index < 4);
          insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
@@ -1626,6 +1627,7 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
     case sve_shift_pred:
     case sve_shift_unpred:
     case sve_shift_tsz_hsd:
+    case sve_shift_tsz_bhsd:
       /* For indices and shift amounts, the variant is encoded as
         part of the immediate.  */
       break;
@@ -1672,8 +1674,14 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
                    aarch64_get_variant (inst) + 1, 0);
       break;
 
-    case sve_size_013:
-      variant = aarch64_get_variant (inst);
+    case sve_size_tsz_bhs:
+      insert_fields (&inst->value,
+                    (1 << aarch64_get_variant (inst)),
+                    0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+      break;
+
+    case sve_size_13:
+      variant = aarch64_get_variant (inst) + 1;
       if (variant == 2)
          variant = 3;
       insert_field (FLD_size, &inst->value, variant, 0);