/* aarch64-asm.c -- AArch64 assembler support.
- Copyright (C) 2012-2019 Free Software Foundation, Inc.
+ Copyright (C) 2012-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
/* Operand inserters. */
+/* Insert nothing. */
+bfd_boolean
+aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
+ aarch64_insn *code ATTRIBUTE_UNUSED,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ return TRUE;
+}
+
/* Insert register number. */
bfd_boolean
aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
switch (info->qualifier)
{
case AARCH64_OPND_QLF_S_4B:
+ case AARCH64_OPND_QLF_S_2H:
/* L:H */
assert (reglane_index < 4);
insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
const aarch64_opnd_info *prev_operand;
unsigned int esize;
- assert (info->idx > 0);
- prev_operand = &inst->operands[info->idx - 1];
+ unsigned int opnd_backshift = get_operand_specific_data (self);
+ assert (info->idx >= (int)opnd_backshift);
+ prev_operand = &inst->operands[info->idx - opnd_backshift];
esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
insert_all_fields (self, code, 16 * esize - info->imm.value);
return TRUE;
static void
aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
{
+ int variant = 0;
switch (inst->opcode->iclass)
{
case sve_cpy:
case sve_index:
case sve_shift_pred:
case sve_shift_unpred:
+ case sve_shift_tsz_hsd:
+ case sve_shift_tsz_bhsd:
/* For indices and shift amounts, the variant is encoded as
part of the immediate. */
break;
insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
break;
+ case sve_size_bh:
case sve_size_sd:
insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
break;
aarch64_get_variant (inst) + 1, 0);
break;
+ case sve_size_tsz_bhs:
+ insert_fields (&inst->value,
+ (1 << aarch64_get_variant (inst)),
+ 0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
+ break;
+
+ case sve_size_13:
+ variant = aarch64_get_variant (inst) + 1;
+ if (variant == 2)
+ variant = 3;
+ insert_field (FLD_size, &inst->value, variant, 0);
+ break;
+
default:
break;
}
break;
}
-convert_to_real_return:
+ convert_to_real_return:
aarch64_replace_opcode (inst, real);
}
}
-encoding_exit:
+ encoding_exit:
DEBUG_TRACE ("exit with %s", opcode->name);
*code = inst->value;