x86: don't accept FI{LD,STP,STTP}LL in Intel syntax mode

[deliverable/binutils-gdb.git] / opcodes / aarch64-asm.c

diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index afb0e5b4d2ad0e62307e97858062f8599169248e..fc70ffcc7b6324fe8a174b0fd9ba9709a3fd2284 100644 (file)
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1,5 +1,5 @@
 /* aarch64-asm.c -- AArch64 assembler support.
-   Copyright (C) 2012-2019 Free Software Foundation, Inc.
+   Copyright (C) 2012-2020 Free Software Foundation, Inc.
    Contributed by ARM Ltd.
 
    This file is part of the GNU opcodes library.
@@ -130,6 +130,7 @@ aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
       switch (info->qualifier)
        {
        case AARCH64_OPND_QLF_S_4B:
+       case AARCH64_OPND_QLF_S_2H:
          /* L:H */
          assert (reglane_index < 4);
          insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
@@ -1679,8 +1680,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
                     0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
       break;
 
-    case sve_size_013:
-      variant = aarch64_get_variant (inst);
+    case sve_size_13:
+      variant = aarch64_get_variant (inst) + 1;
       if (variant == 2)
          variant = 3;
       insert_field (FLD_size, &inst->value, variant, 0);
@@ -1966,7 +1967,7 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real)
       break;
     }
 
-convert_to_real_return:
+ convert_to_real_return:
   aarch64_replace_opcode (inst, real);
 }
 
@@ -2098,7 +2099,7 @@ aarch64_opcode_encode (const aarch64_opcode *opcode,
     }
 
 
-encoding_exit:
+ encoding_exit:
   DEBUG_TRACE ("exit with %s", opcode->name);
 
   *code = inst->value;