[AArch64][SVE 26/32] Add SVE MUL VL addressing modes

[deliverable/binutils-gdb.git] / opcodes / aarch64-dis-2.c

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 3dd714f4f650e7be63d505787c87b8de373344db..48d6ce7fefd2ee11ec92c520e259adf6c9a7b7cb 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10426,12 +10426,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 27:
     case 35:
     case 36:
-    case 123:
-    case 124:
-    case 125:
-    case 126:
-    case 127:
-    case 128:
     case 129:
     case 130:
     case 131:
@@ -10440,7 +10434,13 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 134:
     case 135:
     case 136:
+    case 137:
+    case 138:
     case 139:
+    case 140:
+    case 141:
+    case 142:
+    case 145:
       return aarch64_ext_regno (self, info, code, inst);
     case 8:
       return aarch64_ext_regrt_sysins (self, info, code, inst);
@@ -10482,8 +10482,8 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 68:
     case 69:
     case 70:
-    case 120:
-    case 122:
+    case 126:
+    case 128:
       return aarch64_ext_imm (self, info, code, inst);
     case 38:
     case 39:
@@ -10540,46 +10540,55 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 90:
     case 91:
     case 92:
-      return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst);
+      return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst);
     case 93:
+      return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst);
     case 94:
+      return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst);
     case 95:
     case 96:
     case 97:
     case 98:
+      return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst);
     case 99:
     case 100:
     case 101:
     case 102:
     case 103:
     case 104:
-      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst);
     case 105:
     case 106:
     case 107:
     case 108:
     case 109:
     case 110:
+      return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst);
     case 111:
     case 112:
-      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst);
     case 113:
     case 114:
     case 115:
     case 116:
-      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst);
     case 117:
-      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst);
     case 118:
-      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst);
+      return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst);
     case 119:
-      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst);
+    case 120:
     case 121:
+    case 122:
+      return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst);
+    case 123:
+      return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst);
+    case 124:
+      return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst);
+    case 125:
+      return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst);
+    case 127:
       return aarch64_ext_sve_scale (self, info, code, inst);
-    case 137:
+    case 143:
       return aarch64_ext_sve_index (self, info, code, inst);
-    case 138:
-    case 140:
+    case 144:
+    case 146:
       return aarch64_ext_sve_reglist (self, info, code, inst);
     default: assert (0); abort ();
     }