[BINUTILS, AArch64] Enable Transactional Memory Extension

[deliverable/binutils-gdb.git] / opcodes / aarch64-opc-2.c

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 6902136e147e00d33317b5de963a2fb5784d6984..96eedd72c7514203449805825e0293b41221f607 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -223,6 +223,7 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
   {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
+  {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
   {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
   {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
 };
@@ -301,17 +302,17 @@ static const unsigned op_enum_table [] =
   391,
   413,
   415,
-  1254,
-  1259,
-  1252,
-  1251,
+  1258,
+  1263,
+  1256,
   1255,
-  1262,
-  1264,
-  1265,
-  1261,
-  1267,
+  1259,
   1266,
+  1268,
+  1269,
+  1265,
+  1271,
+  1270,
   131,
 };