/* aarch64-opc.c -- AArch64 opcode support.
- Copyright (C) 2009-2019 Free Software Foundation, Inc.
+ Copyright (C) 2009-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
assert (width < 32);
if (width < sizeof (value) * 8)
{
- int64_t lim = (int64_t)1 << (width - 1);
+ int64_t lim = (uint64_t) 1 << (width - 1);
if (value >= -lim && value < lim)
return 1;
}
assert (width < 32);
if (width < sizeof (value) * 8)
{
- int64_t lim = (int64_t)1 << width;
+ int64_t lim = (uint64_t) 1 << width;
if (value >= 0 && value < lim)
return 1;
}
{8, 1, 0x3, "d", OQK_OPD_VARIANT},
{16, 1, 0x4, "q", OQK_OPD_VARIANT},
{4, 1, 0x0, "4b", OQK_OPD_VARIANT},
+ {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
{1, 4, 0x0, "4b", OQK_OPD_VARIANT},
{1, 8, 0x0, "8b", OQK_OPD_VARIANT},
amount will be returned in *SHIFT_AMOUNT. */
bfd_boolean
-aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
+aarch64_wide_constant_p (uint64_t value, int is32, unsigned int *shift_amount)
{
int amount;
/* Allow all zeros or all ones in top 32-bits, so that
32-bit constant expressions like ~0x80000000 are
permitted. */
- uint64_t ext = value;
- if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
+ if (value >> 32 != 0 && value >> 32 != 0xffffffff)
/* Immediate out of range. */
return FALSE;
- value &= (int64_t) 0xffffffff;
+ value &= 0xffffffff;
}
/* first, try movz then movn */
amount = -1;
- if ((value & ((int64_t) 0xffff << 0)) == value)
+ if ((value & ((uint64_t) 0xffff << 0)) == value)
amount = 0;
- else if ((value & ((int64_t) 0xffff << 16)) == value)
+ else if ((value & ((uint64_t) 0xffff << 16)) == value)
amount = 16;
- else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
+ else if (!is32 && (value & ((uint64_t) 0xffff << 32)) == value)
amount = 32;
- else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
+ else if (!is32 && (value & ((uint64_t) 0xffff << 48)) == value)
amount = 48;
if (amount == -1)
: _("z0-z7 expected"));
return 0;
}
- mask = (1 << (size - shift)) - 1;
+ mask = (1u << (size - shift)) - 1;
if (!value_in_range_p (opnd->reglane.index, 0, mask))
{
set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
break;
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
min_value = -8;
max_value = 7;
goto sve_imm_offset;
if (!value_fit_unsigned_field_p (opnd->imm.value, size))
{
set_imm_out_of_range_error (mismatch_detail, idx, 0,
- (1 << size) - 1);
+ (1u << size) - 1);
return 0;
}
break;
case AARCH64_OPND_SVE_SHRIMM_PRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED:
case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
+ num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
+ size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier);
+ if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
{
- unsigned int index =
- (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
- size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier);
- if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
- {
- set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
- return 0;
- }
- break;
- }
+ set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
+ return 0;
+ }
+ break;
default:
break;
if (opnd->addr.writeback)
{
if (opnd->addr.preind)
- snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+ {
+ if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
+ snprintf (buf, size, "[%s]!", base);
+ else
+ snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
+ }
else
snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
}
case AARCH64_OPND_ADDR_SIMM13:
case AARCH64_OPND_ADDR_OFFSET:
case AARCH64_OPND_SVE_ADDR_RI_S4x16:
+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
{ "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
{ "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
{ "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
- { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
- { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
- { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
- { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
- { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
+ { "tfsre0_el1", CPENC(3,0,C5,C6,1), F_ARCHEXT },
+ { "tfsr_el1", CPENC(3,0,C5,C6,0), F_ARCHEXT },
+ { "tfsr_el2", CPENC(3,4,C5,C6,0), F_ARCHEXT },
+ { "tfsr_el3", CPENC(3,6,C5,C6,0), F_ARCHEXT },
+ { "tfsr_el12", CPENC(3,5,C5,C6,0), F_ARCHEXT },
{ "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
{ "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
{ "gmid_el1", CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
/* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
if ((reg->value == CPENC (3, 3, C4, C2, 7)
- || reg->value == CPENC (3, 0, C6, C6, 1)
- || reg->value == CPENC (3, 0, C6, C5, 0)
- || reg->value == CPENC (3, 4, C6, C5, 0)
- || reg->value == CPENC (3, 6, C6, C6, 0)
- || reg->value == CPENC (3, 5, C6, C6, 0)
+ || reg->value == CPENC (3, 0, C5, C6, 1)
+ || reg->value == CPENC (3, 0, C5, C6, 0)
+ || reg->value == CPENC (3, 4, C5, C6, 0)
+ || reg->value == CPENC (3, 6, C5, C6, 0)
+ || reg->value == CPENC (3, 5, C5, C6, 0)
|| reg->value == CPENC (3, 0, C1, C0, 5)
|| reg->value == CPENC (3, 0, C1, C0, 6)
|| reg->value == CPENC (3, 1, C0, C0, 4))