/* aarch64-opc.c -- AArch64 opcode support.
- Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc.
+ Copyright (C) 2009-2015 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
{ 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
{ 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
{ 31, 1 }, /* sf: in integer data processing instructions. */
+ { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
{ 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
{ 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
{ 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
switch (aarch64_operands[type].op_class)
{
case AARCH64_OPND_CLASS_INT_REG:
+ /* Check pair reg constraints for cas* instructions. */
+ if (type == AARCH64_OPND_PAIRREG)
+ {
+ assert (idx == 1 || idx == 3);
+ if (opnds[idx - 1].reg.regno % 2 != 0)
+ {
+ set_syntax_error (mismatch_detail, idx - 1,
+ _("reg pair must start from even reg"));
+ return 0;
+ }
+ if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
+ {
+ set_syntax_error (mismatch_detail, idx,
+ _("reg pair must be contiguous"));
+ return 0;
+ }
+ break;
+ }
+
/* <Xt> may be optional in some IC and TLBI instructions. */
if (type == AARCH64_OPND_Rt_SYS)
{
{
case AARCH64_OPND_PSTATEFIELD:
assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
+ /* MSR PAN, #uimm4
+ The immediate must be #0 or #1. */
+ if (opnd->pstatefield == 0x04 /* PAN. */
+ && opnds[1].imm.value > 1)
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
+ return 0;
+ }
/* MSR SPSel, #uimm4
Uses uimm4 as a control value to select the stack pointer: if
bit 0 is set it selects the current exception level's stack
else
tb[0] = '\0';
- snprintf (buf, size, "[%s,%c%d%s]",
+ snprintf (buf, size, "[%s,%s%s]",
get_64bit_int_reg_name (opnd->addr.base_regno, 1),
- wm_p ? 'w' : 'x', opnd->addr.offset.regno, tb);
+ get_int_reg_name (opnd->addr.offset.regno,
+ wm_p ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X,
+ 0 /* sp_reg_p */),
+ tb);
}
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
case AARCH64_OPND_Rs:
case AARCH64_OPND_Ra:
case AARCH64_OPND_Rt_SYS:
+ case AARCH64_OPND_PAIRREG:
/* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
the <ic_op>, therefore we we use opnd->present to override the
generic optional-ness information. */
case AARCH64_OPND_SYSREG_DC:
case AARCH64_OPND_SYSREG_IC:
case AARCH64_OPND_SYSREG_TLBI:
- snprintf (buf, size, "%s", opnd->sysins_op->template);
+ snprintf (buf, size, "%s", opnd->sysins_op->name);
break;
case AARCH64_OPND_BARRIER:
#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
/* for 3.9.10 System Instructions */
#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
-/* Trace unit registers. */
-#define CPENT(crn,crm,op2) CPENC(2,1,(crn),(crm),(op2))
#define C0 0
#define C1 1
#ifdef F_DEPRECATED
#undef F_DEPRECATED
#endif
+#define F_DEPRECATED 0x1 /* Deprecated system register. */
-#ifdef F_READONLY
-#undef F_READONLY
-#endif
-
-#ifdef F_WRITEONLY
-#undef F_WRITEONLY
+#ifdef F_ARCHEXT
+#undef F_ARCHEXT
#endif
+#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
-#define F_DEPRECATED 0x1 /* Deprecated system register. */
-#define F_READONLY 0x2 /* Not for MSR. */
-#define F_WRITEONLY 0x4 /* Not for MRS. */
/* TODO there are two more issues need to be resolved
1. handle read-only and write-only system registers
const aarch64_sys_reg aarch64_sys_regs [] =
{
{ "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
+ { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
{ "elr_el1", CPEN_(0,C0,1), 0 },
+ { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
{ "sp_el0", CPEN_(0,C1,0), 0 },
{ "spsel", CPEN_(0,C2,0), 0 },
{ "daif", CPEN_(3,C2,1), 0 },
{ "currentel", CPEN_(0,C2,2), 0 }, /* RO */
+ { "pan", CPEN_(0,C2,3), F_ARCHEXT },
{ "nzcv", CPEN_(3,C2,0), 0 },
{ "fpcr", CPEN_(3,C4,0), 0 },
{ "fpsr", CPEN_(3,C4,1), 0 },
{ "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */
{ "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */
{ "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */
+ { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), 0 }, /* RO */
{ "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */
{ "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */
{ "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */
{ "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
{ "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
{ "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
+ { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
{ "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
{ "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
{ "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
{ "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
+ { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
{ "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
{ "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
{ "scr_el3", CPENC(3,6,C1,C1,0), 0 },
{ "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
{ "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
{ "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
+ { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
{ "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
+ { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
+ { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
{ "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
{ "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
{ "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
{ "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
+ { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
{ "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
{ "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
{ "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
{ "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
{ "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
{ "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
+ { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
{ "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
+ { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
{ "esr_el1", CPENC(3,0,C5,C2,0), 0 },
{ "esr_el2", CPENC(3,4,C5,C2,0), 0 },
{ "esr_el3", CPENC(3,6,C5,C2,0), 0 },
+ { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
{ "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
{ "far_el1", CPENC(3,0,C6,C0,0), 0 },
{ "far_el2", CPENC(3,4,C6,C0,0), 0 },
{ "far_el3", CPENC(3,6,C6,C0,0), 0 },
+ { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
{ "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
{ "par_el1", CPENC(3,0,C7,C4,0), 0 },
{ "mair_el1", CPENC(3,0,C10,C2,0), 0 },
{ "mair_el2", CPENC(3,4,C10,C2,0), 0 },
{ "mair_el3", CPENC(3,6,C10,C2,0), 0 },
+ { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
{ "amair_el1", CPENC(3,0,C10,C3,0), 0 },
{ "amair_el2", CPENC(3,4,C10,C3,0), 0 },
{ "amair_el3", CPENC(3,6,C10,C3,0), 0 },
+ { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
{ "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
{ "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
{ "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
+ { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
{ "rvbar_el1", CPENC(3,0,C12,C0,1), 0 }, /* RO */
{ "rvbar_el2", CPENC(3,4,C12,C0,1), 0 }, /* RO */
{ "rvbar_el3", CPENC(3,6,C12,C0,1), 0 }, /* RO */
{ "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
{ "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
{ "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
+ { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
+ { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
{ "cntvct_el0", CPENC(3,3,C14,C0,2), 0 }, /* RO */
{ "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
{ "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
+ { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
{ "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
{ "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
+ { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
{ "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
+ { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
{ "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
+ { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
{ "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
+ { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
{ "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
+ { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
{ "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
+ { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
{ "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
{ "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
{ "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
{ "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
{ "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
{ "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
+ { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
+ { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
+ { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
{ "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
{ "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
{ "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
{ "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
{ "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
{ "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
- /* Trace unit registers. */
- { "trcprgctlr", CPENT(C0,C1,0), 0 },
- { "trcprocselr", CPENT(C0,C2,0), 0 },
- { "trcstatr", CPENT(C0,C3,0), F_READONLY },
- { "trcconfigr", CPENT(C0,C4,0), 0 },
- { "trcauxctlr", CPENT(C0,C6,0), 0 },
- { "trceventctl0r", CPENT(C0,C8,0), 0 },
- { "trceventctl1r", CPENT(C0,C9,0), 0 },
- { "trcstallctlr", CPENT(C0,C11,0), 0 },
- { "trctsctlr", CPENT(C0,C12,0), 0 },
- { "trcsyncpr", CPENT(C0,C13,0), 0 },
- { "trcccctlr", CPENT(C0,C14,0), 0 },
- { "trcbbctlr", CPENT(C0,C15,0), 0 },
- { "trctraceidr", CPENT(C0,C0,1), 0 },
- { "trcqctlr", CPENT(C0,C1,1), 0 },
- { "trcvictlr", CPENT(C0,C0,2), 0 },
- { "trcviiectlr", CPENT(C0,C1,2), 0 },
- { "trcvissctlr", CPENT(C0,C2,2), 0 },
- { "trcvipcssctlr", CPENT(C0,C3,2), 0 },
- { "trcvdctlr", CPENT(C0,C8,2), 0 },
- { "trcvdsacctlr", CPENT(C0,C9,2), 0 },
- { "trcvdarcctlr", CPENT(C0,C10,2), 0 },
- { "trcseqevr0", CPENT(C0,C0,4), 0 },
- { "trcseqevr1", CPENT(C0,C1,4), 0 },
- { "trcseqevr2", CPENT(C0,C2,4), 0 },
- { "trcseqrstevr", CPENT(C0,C6,4), 0 },
- { "trcseqstr", CPENT(C0,C7,4), 0 },
- { "trcextinselr", CPENT(C0,C8,4), 0 },
- { "trccntrldvr0", CPENT(C0,C0,5), 0 },
- { "trccntrldvr1", CPENT(C0,C1,5), 0 },
- { "trccntrldvr2", CPENT(C0,C2,5), 0 },
- { "trccntrldvr3", CPENT(C0,C3,5), 0 },
- { "trccntctlr0", CPENT(C0,C4,5), 0 },
- { "trccntctlr1", CPENT(C0,C5,5), 0 },
- { "trccntctlr2", CPENT(C0,C6,5), 0 },
- { "trccntctlr3", CPENT(C0,C7,5), 0 },
- { "trccntvr0", CPENT(C0,C8,5), 0 },
- { "trccntvr1", CPENT(C0,C9,5), 0 },
- { "trccntvr2", CPENT(C0,C10,5), 0 },
- { "trccntvr3", CPENT(C0,C11,5), 0 },
- { "trcidr8", CPENT(C0,C0,6), F_READONLY },
- { "trcidr9", CPENT(C0,C1,6), F_READONLY },
- { "trcidr10", CPENT(C0,C2,6), F_READONLY },
- { "trcidr11", CPENT(C0,C3,6), F_READONLY },
- { "trcidr12", CPENT(C0,C4,6), F_READONLY },
- { "trcidr13", CPENT(C0,C5,6), F_READONLY },
- { "trcimspec0", CPENT(C0,C0,7), 0 },
- { "trcimspec1", CPENT(C0,C1,7), 0 },
- { "trcimspec2", CPENT(C0,C2,7), 0 },
- { "trcimspec3", CPENT(C0,C3,7), 0 },
- { "trcimspec4", CPENT(C0,C4,7), 0 },
- { "trcimspec5", CPENT(C0,C5,7), 0 },
- { "trcimspec6", CPENT(C0,C6,7), 0 },
- { "trcimspec7", CPENT(C0,C7,7), 0 },
- { "trcidr0", CPENT(C0,C8,7), F_READONLY },
- { "trcidr1", CPENT(C0,C9,7), F_READONLY },
- { "trcidr2", CPENT(C0,C10,7), F_READONLY },
- { "trcidr3", CPENT(C0,C11,7), F_READONLY },
- { "trcidr4", CPENT(C0,C12,7), F_READONLY },
- { "trcidr5", CPENT(C0,C13,7), F_READONLY },
- { "trcidr6", CPENT(C0,C14,7), F_READONLY },
- { "trcidr7", CPENT(C0,C15,7), F_READONLY },
- { "trcrsctlr2", CPENT(C1,C2,0), 0 },
- { "trcrsctlr3", CPENT(C1,C3,0), 0 },
- { "trcrsctlr4", CPENT(C1,C4,0), 0 },
- { "trcrsctlr5", CPENT(C1,C5,0), 0 },
- { "trcrsctlr6", CPENT(C1,C6,0), 0 },
- { "trcrsctlr7", CPENT(C1,C7,0), 0 },
- { "trcrsctlr8", CPENT(C1,C8,0), 0 },
- { "trcrsctlr9", CPENT(C1,C9,0), 0 },
- { "trcrsctlr10", CPENT(C1,C10,0), 0 },
- { "trcrsctlr11", CPENT(C1,C11,0), 0 },
- { "trcrsctlr12", CPENT(C1,C12,0), 0 },
- { "trcrsctlr13", CPENT(C1,C13,0), 0 },
- { "trcrsctlr14", CPENT(C1,C14,0), 0 },
- { "trcrsctlr15", CPENT(C1,C15,0), 0 },
- { "trcrsctlr16", CPENT(C1,C0,1), 0 },
- { "trcrsctlr17", CPENT(C1,C1,1), 0 },
- { "trcrsctlr18", CPENT(C1,C2,1), 0 },
- { "trcrsctlr19", CPENT(C1,C3,1), 0 },
- { "trcrsctlr20", CPENT(C1,C4,1), 0 },
- { "trcrsctlr21", CPENT(C1,C5,1), 0 },
- { "trcrsctlr22", CPENT(C1,C6,1), 0 },
- { "trcrsctlr23", CPENT(C1,C7,1), 0 },
- { "trcrsctlr24", CPENT(C1,C8,1), 0 },
- { "trcrsctlr25", CPENT(C1,C9,1), 0 },
- { "trcrsctlr26", CPENT(C1,C10,1), 0 },
- { "trcrsctlr27", CPENT(C1,C11,1), 0 },
- { "trcrsctlr28", CPENT(C1,C12,1), 0 },
- { "trcrsctlr29", CPENT(C1,C13,1), 0 },
- { "trcrsctlr30", CPENT(C1,C14,1), 0 },
- { "trcrsctlr31", CPENT(C1,C15,1), 0 },
- { "trcssccr0", CPENT(C1,C0,2), 0 },
- { "trcssccr1", CPENT(C1,C1,2), 0 },
- { "trcssccr2", CPENT(C1,C2,2), 0 },
- { "trcssccr3", CPENT(C1,C3,2), 0 },
- { "trcssccr4", CPENT(C1,C4,2), 0 },
- { "trcssccr5", CPENT(C1,C5,2), 0 },
- { "trcssccr6", CPENT(C1,C6,2), 0 },
- { "trcssccr7", CPENT(C1,C7,2), 0 },
- { "trcsscsr0", CPENT(C1,C8,2), 0 },
- { "trcsscsr1", CPENT(C1,C9,2), 0 },
- { "trcsscsr2", CPENT(C1,C10,2), 0 },
- { "trcsscsr3", CPENT(C1,C11,2), 0 },
- { "trcsscsr4", CPENT(C1,C12,2), 0 },
- { "trcsscsr5", CPENT(C1,C13,2), 0 },
- { "trcsscsr6", CPENT(C1,C14,2), 0 },
- { "trcsscsr7", CPENT(C1,C15,2), 0 },
- { "trcsspcicr0", CPENT(C1,C0,3), 0 },
- { "trcsspcicr1", CPENT(C1,C1,3), 0 },
- { "trcsspcicr2", CPENT(C1,C2,3), 0 },
- { "trcsspcicr3", CPENT(C1,C3,3), 0 },
- { "trcsspcicr4", CPENT(C1,C4,3), 0 },
- { "trcsspcicr5", CPENT(C1,C5,3), 0 },
- { "trcsspcicr6", CPENT(C1,C6,3), 0 },
- { "trcsspcicr7", CPENT(C1,C7,3), 0 },
- { "trcoslar", CPENT(C1,C0,4), F_WRITEONLY },
- { "trcoslsr", CPENT(C1,C1,4), F_READONLY },
- { "trcpdcr", CPENT(C1,C4,4), 0 },
- { "trcpdsr", CPENT(C1,C5,4), F_READONLY },
- { "trcacvr0", CPENT(C2,C0,0), 0 },
- { "trcacvr1", CPENT(C2,C2,0), 0 },
- { "trcacvr2", CPENT(C2,C4,0), 0 },
- { "trcacvr3", CPENT(C2,C6,0), 0 },
- { "trcacvr4", CPENT(C2,C8,0), 0 },
- { "trcacvr5", CPENT(C2,C10,0), 0 },
- { "trcacvr6", CPENT(C2,C12,0), 0 },
- { "trcacvr7", CPENT(C2,C14,0), 0 },
- { "trcacvr8", CPENT(C2,C0,1), 0 },
- { "trcacvr9", CPENT(C2,C2,1), 0 },
- { "trcacvr10", CPENT(C2,C4,1), 0 },
- { "trcacvr11", CPENT(C2,C6,1), 0 },
- { "trcacvr12", CPENT(C2,C8,1), 0 },
- { "trcacvr13", CPENT(C2,C10,1), 0 },
- { "trcacvr14", CPENT(C2,C12,1), 0 },
- { "trcacvr15", CPENT(C2,C14,1), 0 },
- { "trcacatr0", CPENT(C2,C0,2), 0 },
- { "trcacatr1", CPENT(C2,C2,2), 0 },
- { "trcacatr2", CPENT(C2,C4,2), 0 },
- { "trcacatr3", CPENT(C2,C6,2), 0 },
- { "trcacatr4", CPENT(C2,C8,2), 0 },
- { "trcacatr5", CPENT(C2,C10,2), 0 },
- { "trcacatr6", CPENT(C2,C12,2), 0 },
- { "trcacatr7", CPENT(C2,C14,2), 0 },
- { "trcacatr8", CPENT(C2,C0,3), 0 },
- { "trcacatr9", CPENT(C2,C2,3), 0 },
- { "trcacatr10", CPENT(C2,C4,3), 0 },
- { "trcacatr11", CPENT(C2,C6,3), 0 },
- { "trcacatr12", CPENT(C2,C8,3), 0 },
- { "trcacatr13", CPENT(C2,C10,3), 0 },
- { "trcacatr14", CPENT(C2,C12,3), 0 },
- { "trcacatr15", CPENT(C2,C14,3), 0 },
- { "trcdvcvr0", CPENT(C2,C0,4), 0 },
- { "trcdvcvr1", CPENT(C2,C4,4), 0 },
- { "trcdvcvr2", CPENT(C2,C8,4), 0 },
- { "trcdvcvr3", CPENT(C2,C12,4), 0 },
- { "trcdvcvr4", CPENT(C2,C0,5), 0 },
- { "trcdvcvr5", CPENT(C2,C4,5), 0 },
- { "trcdvcvr6", CPENT(C2,C8,5), 0 },
- { "trcdvcvr7", CPENT(C2,C12,5), 0 },
- { "trcdvcmr0", CPENT(C2,C0,6), 0 },
- { "trcdvcmr1", CPENT(C2,C4,6), 0 },
- { "trcdvcmr2", CPENT(C2,C8,6), 0 },
- { "trcdvcmr3", CPENT(C2,C12,6), 0 },
- { "trcdvcmr4", CPENT(C2,C0,7), 0 },
- { "trcdvcmr5", CPENT(C2,C4,7), 0 },
- { "trcdvcmr6", CPENT(C2,C8,7), 0 },
- { "trcdvcmr7", CPENT(C2,C12,7), 0 },
- { "trccidcvr0", CPENT(C3,C0,0), 0 },
- { "trccidcvr1", CPENT(C3,C2,0), 0 },
- { "trccidcvr2", CPENT(C3,C4,0), 0 },
- { "trccidcvr3", CPENT(C3,C6,0), 0 },
- { "trccidcvr4", CPENT(C3,C8,0), 0 },
- { "trccidcvr5", CPENT(C3,C10,0), 0 },
- { "trccidcvr6", CPENT(C3,C12,0), 0 },
- { "trccidcvr7", CPENT(C3,C14,0), 0 },
- { "trcvmidcvr0", CPENT(C3,C0,1), 0 },
- { "trcvmidcvr1", CPENT(C3,C2,1), 0 },
- { "trcvmidcvr2", CPENT(C3,C4,1), 0 },
- { "trcvmidcvr3", CPENT(C3,C6,1), 0 },
- { "trcvmidcvr4", CPENT(C3,C8,1), 0 },
- { "trcvmidcvr5", CPENT(C3,C10,1), 0 },
- { "trcvmidcvr6", CPENT(C3,C12,1), 0 },
- { "trcvmidcvr7", CPENT(C3,C14,1), 0 },
- { "trccidcctlr0", CPENT(C3,C0,2), 0 },
- { "trccidcctlr1", CPENT(C3,C1,2), 0 },
- { "trcvmidcctlr0", CPENT(C3,C2,2), 0 },
- { "trcvmidcctlr1", CPENT(C3,C3,2), 0 },
- { "trcitctrl", CPENT(C7,C0,4), 0 },
- { "trcclaimset", CPENT(C7,C8,6), 0 },
- { "trcclaimclr", CPENT(C7,C9,6), 0 },
- { "trcdevaff0", CPENT(C7,C10,6), F_READONLY },
- { "trcdevaff1", CPENT(C7,C11,6), F_READONLY },
- { "trclar", CPENT(C7,C12,6), F_WRITEONLY },
- { "trclsr", CPENT(C7,C13,6), F_READONLY },
- { "trcauthstatus", CPENT(C7,C14,6), F_READONLY },
- { "trcdevarch", CPENT(C7,C15,6), F_READONLY },
- { "trcdevid", CPENT(C7,C2,7), F_READONLY },
- { "trcdevtype", CPENT(C7,C3,7), F_READONLY },
- { "trcpidr4", CPENT(C7,C4,7), F_READONLY },
- { "trcpidr5", CPENT(C7,C5,7), F_READONLY },
- { "trcpidr6", CPENT(C7,C6,7), F_READONLY },
- { "trcpidr7", CPENT(C7,C7,7), F_READONLY },
- { "trcpidr0", CPENT(C7,C8,7), F_READONLY },
- { "trcpidr1", CPENT(C7,C9,7), F_READONLY },
- { "trcpidr2", CPENT(C7,C10,7), F_READONLY },
- { "trcpidr3", CPENT(C7,C11,7), F_READONLY },
- { "trccidr0", CPENT(C7,C12,7), F_READONLY },
- { "trccidr1", CPENT(C7,C13,7), F_READONLY },
- { "trccidr2", CPENT(C7,C14,7), F_READONLY },
- { "trccidr3", CPENT(C7,C15,7), F_READONLY },
{ 0, CPENC(0,0,0,0,0), 0 },
};
}
bfd_boolean
-aarch64_sys_reg_readonly_p (const aarch64_sys_reg *reg)
-{
- return (reg->flags & F_READONLY) != 0;
-}
+aarch64_sys_reg_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* PAN. Values are from aarch64_sys_regs. */
+ if (reg->value == CPEN_(0,C2,3)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
+ return FALSE;
+
+ /* Virtualization host extensions: system registers. */
+ if ((reg->value == CPENC (3, 4, C2, C0, 1)
+ || reg->value == CPENC (3, 4, C13, C0, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 0)
+ || reg->value == CPENC (3, 4, C14, C3, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
-bfd_boolean
-aarch64_sys_reg_writeonly_p (const aarch64_sys_reg *reg)
-{
- return (reg->flags & F_WRITEONLY) != 0;
+ /* Virtualization host extensions: *_el12 names of *_el1 registers. */
+ if ((reg->value == CPEN_ (5, C0, 0)
+ || reg->value == CPEN_ (5, C0, 1)
+ || reg->value == CPENC (3, 5, C1, C0, 0)
+ || reg->value == CPENC (3, 5, C1, C0, 2)
+ || reg->value == CPENC (3, 5, C2, C0, 0)
+ || reg->value == CPENC (3, 5, C2, C0, 1)
+ || reg->value == CPENC (3, 5, C2, C0, 2)
+ || reg->value == CPENC (3, 5, C5, C1, 0)
+ || reg->value == CPENC (3, 5, C5, C1, 1)
+ || reg->value == CPENC (3, 5, C5, C2, 0)
+ || reg->value == CPENC (3, 5, C6, C0, 0)
+ || reg->value == CPENC (3, 5, C10, C2, 0)
+ || reg->value == CPENC (3, 5, C10, C3, 0)
+ || reg->value == CPENC (3, 5, C12, C0, 0)
+ || reg->value == CPENC (3, 5, C13, C0, 1)
+ || reg->value == CPENC (3, 5, C14, C1, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el02 names of *_el0 registers. */
+ if ((reg->value == CPENC (3, 5, C14, C2, 0)
+ || reg->value == CPENC (3, 5, C14, C2, 1)
+ || reg->value == CPENC (3, 5, C14, C2, 2)
+ || reg->value == CPENC (3, 5, C14, C3, 0)
+ || reg->value == CPENC (3, 5, C14, C3, 1)
+ || reg->value == CPENC (3, 5, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ return TRUE;
}
-const struct aarch64_name_value_pair aarch64_pstatefields [] =
+const aarch64_sys_reg aarch64_pstatefields [] =
{
- { "spsel", 0x05 },
- { "daifset", 0x1e },
- { "daifclr", 0x1f },
- { 0, CPENC(0,0,0,0,0) },
+ { "spsel", 0x05, 0 },
+ { "daifset", 0x1e, 0 },
+ { "daifclr", 0x1f, 0 },
+ { "pan", 0x04, F_ARCHEXT },
+ { 0, CPENC(0,0,0,0,0), 0 },
};
+bfd_boolean
+aarch64_pstatefield_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* PAN. Values are from aarch64_pstatefields. */
+ if (reg->value == 0x04
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
+ return FALSE;
+
+ return TRUE;
+}
+
const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
{
{ "ialluis", CPENS(0,C7,C1,0), 0 },
projects / deliverable / binutils-gdb.git / blobdiff