{
case AARCH64_OPND_PSTATEFIELD:
assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
+ /* MSR PAN, #uimm4
+ The immediate must be #0 or #1. */
+ if (opnd->pstatefield == 0x04 /* PAN. */
+ && opnds[1].imm.value > 1)
+ {
+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
+ return 0;
+ }
/* MSR SPSel, #uimm4
Uses uimm4 as a control value to select the stack pointer: if
bit 0 is set it selects the current exception level's stack
case AARCH64_OPND_SYSREG_DC:
case AARCH64_OPND_SYSREG_IC:
case AARCH64_OPND_SYSREG_TLBI:
- snprintf (buf, size, "%s", opnd->sysins_op->template);
+ snprintf (buf, size, "%s", opnd->sysins_op->name);
break;
case AARCH64_OPND_BARRIER:
#endif
#define F_DEPRECATED 0x1 /* Deprecated system register. */
+#ifdef F_ARCHEXT
+#undef F_ARCHEXT
+#endif
+#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
+
+
/* TODO there are two more issues need to be resolved
1. handle read-only and write-only system registers
2. handle cpu-implementation-defined system registers. */
const aarch64_sys_reg aarch64_sys_regs [] =
{
{ "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
+ { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
{ "elr_el1", CPEN_(0,C0,1), 0 },
+ { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
{ "sp_el0", CPEN_(0,C1,0), 0 },
{ "spsel", CPEN_(0,C2,0), 0 },
{ "daif", CPEN_(3,C2,1), 0 },
{ "currentel", CPEN_(0,C2,2), 0 }, /* RO */
+ { "pan", CPEN_(0,C2,3), F_ARCHEXT },
{ "nzcv", CPEN_(3,C2,0), 0 },
{ "fpcr", CPEN_(3,C4,0), 0 },
{ "fpsr", CPEN_(3,C4,1), 0 },
{ "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */
{ "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */
{ "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */
+ { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), 0 }, /* RO */
{ "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */
{ "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */
{ "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */
{ "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
{ "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
{ "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
+ { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
{ "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
{ "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
{ "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
{ "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
+ { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
{ "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
{ "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
{ "scr_el3", CPENC(3,6,C1,C1,0), 0 },
{ "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
{ "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
{ "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
+ { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
{ "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
+ { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
+ { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
{ "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
{ "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
{ "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
{ "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
+ { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
{ "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
{ "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
{ "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
{ "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
{ "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
{ "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
+ { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
{ "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
+ { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
{ "esr_el1", CPENC(3,0,C5,C2,0), 0 },
{ "esr_el2", CPENC(3,4,C5,C2,0), 0 },
{ "esr_el3", CPENC(3,6,C5,C2,0), 0 },
+ { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
{ "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
{ "far_el1", CPENC(3,0,C6,C0,0), 0 },
{ "far_el2", CPENC(3,4,C6,C0,0), 0 },
{ "far_el3", CPENC(3,6,C6,C0,0), 0 },
+ { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
{ "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
{ "par_el1", CPENC(3,0,C7,C4,0), 0 },
{ "mair_el1", CPENC(3,0,C10,C2,0), 0 },
{ "mair_el2", CPENC(3,4,C10,C2,0), 0 },
{ "mair_el3", CPENC(3,6,C10,C2,0), 0 },
+ { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
{ "amair_el1", CPENC(3,0,C10,C3,0), 0 },
{ "amair_el2", CPENC(3,4,C10,C3,0), 0 },
{ "amair_el3", CPENC(3,6,C10,C3,0), 0 },
+ { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
{ "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
{ "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
{ "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
+ { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
{ "rvbar_el1", CPENC(3,0,C12,C0,1), 0 }, /* RO */
{ "rvbar_el2", CPENC(3,4,C12,C0,1), 0 }, /* RO */
{ "rvbar_el3", CPENC(3,6,C12,C0,1), 0 }, /* RO */
{ "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
{ "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
{ "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
+ { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
+ { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
{ "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
{ "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
{ "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
{ "cntvct_el0", CPENC(3,3,C14,C0,2), 0 }, /* RO */
{ "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
{ "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
+ { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
{ "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
{ "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
+ { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
{ "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
+ { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
{ "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
+ { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
{ "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
+ { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
{ "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
+ { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
{ "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
+ { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
{ "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
{ "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
{ "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
{ "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
{ "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
{ "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
+ { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
+ { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
+ { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
{ "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
{ "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
{ "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
return (reg->flags & F_DEPRECATED) != 0;
}
+bfd_boolean
+aarch64_sys_reg_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* PAN. Values are from aarch64_sys_regs. */
+ if (reg->value == CPEN_(0,C2,3)
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
+ return FALSE;
+
+ /* Virtualization host extensions: system registers. */
+ if ((reg->value == CPENC (3, 4, C2, C0, 1)
+ || reg->value == CPENC (3, 4, C13, C0, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 0)
+ || reg->value == CPENC (3, 4, C14, C3, 1)
+ || reg->value == CPENC (3, 4, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el12 names of *_el1 registers. */
+ if ((reg->value == CPEN_ (5, C0, 0)
+ || reg->value == CPEN_ (5, C0, 1)
+ || reg->value == CPENC (3, 5, C1, C0, 0)
+ || reg->value == CPENC (3, 5, C1, C0, 2)
+ || reg->value == CPENC (3, 5, C2, C0, 0)
+ || reg->value == CPENC (3, 5, C2, C0, 1)
+ || reg->value == CPENC (3, 5, C2, C0, 2)
+ || reg->value == CPENC (3, 5, C5, C1, 0)
+ || reg->value == CPENC (3, 5, C5, C1, 1)
+ || reg->value == CPENC (3, 5, C5, C2, 0)
+ || reg->value == CPENC (3, 5, C6, C0, 0)
+ || reg->value == CPENC (3, 5, C10, C2, 0)
+ || reg->value == CPENC (3, 5, C10, C3, 0)
+ || reg->value == CPENC (3, 5, C12, C0, 0)
+ || reg->value == CPENC (3, 5, C13, C0, 1)
+ || reg->value == CPENC (3, 5, C14, C1, 0))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ /* Virtualization host extensions: *_el02 names of *_el0 registers. */
+ if ((reg->value == CPENC (3, 5, C14, C2, 0)
+ || reg->value == CPENC (3, 5, C14, C2, 1)
+ || reg->value == CPENC (3, 5, C14, C2, 2)
+ || reg->value == CPENC (3, 5, C14, C3, 0)
+ || reg->value == CPENC (3, 5, C14, C3, 1)
+ || reg->value == CPENC (3, 5, C14, C3, 2))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
+
+ return TRUE;
+}
+
const aarch64_sys_reg aarch64_pstatefields [] =
{
{ "spsel", 0x05, 0 },
{ "daifset", 0x1e, 0 },
{ "daifclr", 0x1f, 0 },
+ { "pan", 0x04, F_ARCHEXT },
{ 0, CPENC(0,0,0,0,0), 0 },
};
+bfd_boolean
+aarch64_pstatefield_supported_p (const aarch64_feature_set features,
+ const aarch64_sys_reg *reg)
+{
+ if (!(reg->flags & F_ARCHEXT))
+ return TRUE;
+
+ /* PAN. Values are from aarch64_pstatefields. */
+ if (reg->value == 0x04
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
+ return FALSE;
+
+ return TRUE;
+}
+
const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
{
{ "ialluis", CPENS(0,C7,C1,0), 0 },