/* aarch64-opc.c -- AArch64 opcode support.
- Copyright (C) 2009-2015 Free Software Foundation, Inc.
+ Copyright (C) 2009-2016 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
{1, 8, 0x0, "8b", OQK_OPD_VARIANT},
{1, 16, 0x1, "16b", OQK_OPD_VARIANT},
+ {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
{2, 4, 0x2, "4h", OQK_OPD_VARIANT},
{2, 8, 0x3, "8h", OQK_OPD_VARIANT},
{4, 2, 0x4, "2s", OQK_OPD_VARIANT},
{
case AARCH64_OPND_PSTATEFIELD:
assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
- /* MSR PAN, #uimm4
+ /* MSR UAO, #uimm4
+ MSR PAN, #uimm4
The immediate must be #0 or #1. */
- if (opnd->pstatefield == 0x04 /* PAN. */
+ if ((opnd->pstatefield == 0x03 /* UAO. */
+ || opnd->pstatefield == 0x04) /* PAN. */
&& opnds[1].imm.value > 1)
{
set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
|| reg->value == CPENC (3, 5, C14, C3, 1)
|| reg->value == CPENC (3, 5, C14, C3, 2))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
+ return FALSE;
/* ARMv8.2 features. */
/* RAS extension. */
- /* ERRIDR_EL1 and ERRSELR_EL1. */
- if ((reg->value == CPENC (3, 0, C5, C3, 0)
- || reg->value == CPENC (3, 0, C5, C3, 1))
- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
- return FALSE;
-
- /* ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1, ERXMISC0_EL1 AND
- ERXMISC1_EL1. */
+ /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
+ ERXMISC0_EL1 AND ERXMISC1_EL1. */
if ((reg->value == CPENC (3, 0, C5, C3, 0)
- || reg->value == CPENC (3, 0, C5, C3 ,1)
+ || reg->value == CPENC (3, 0, C5, C3, 1)
|| reg->value == CPENC (3, 0, C5, C3, 2)
|| reg->value == CPENC (3, 0, C5, C3, 3)
+ || reg->value == CPENC (3, 0, C5, C4, 0)
+ || reg->value == CPENC (3, 0, C5, C4, 1)
+ || reg->value == CPENC (3, 0, C5, C4, 2)
+ || reg->value == CPENC (3, 0, C5, C4, 3)
|| reg->value == CPENC (3, 0, C5, C5, 0)
|| reg->value == CPENC (3, 0, C5, C5, 1))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
- /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
- if ((reg->value == CPENS (0, C7, C9, 0)
- || reg->value == CPENS (0, C7, C9, 1))
- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
- return FALSE;
-
return TRUE;
}
&& !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
return FALSE;
+ /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
+ if ((reg->value == CPENS (0, C7, C9, 0)
+ || reg->value == CPENS (0, C7, C9, 1))
+ && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
+ return FALSE;
+
return TRUE;
}