/* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
- Copyright (C) 2012-2014 Free Software Foundation, Inc.
+ Copyright (C) 2012-2020 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
FLD_type,
FLD_ldst_size,
FLD_imm6,
+ FLD_imm6_2,
FLD_imm4,
+ FLD_imm4_2,
+ FLD_imm4_3,
FLD_imm5,
FLD_imm7,
FLD_imm8,
FLD_immr,
FLD_immb,
FLD_immh,
+ FLD_S_imm10,
FLD_N,
FLD_index,
FLD_index2,
FLD_sf,
+ FLD_lse_sz,
FLD_H,
FLD_L,
FLD_M,
FLD_b5,
FLD_b40,
FLD_scale,
+ FLD_SVE_M_4,
+ FLD_SVE_M_14,
+ FLD_SVE_M_16,
+ FLD_SVE_N,
+ FLD_SVE_Pd,
+ FLD_SVE_Pg3,
+ FLD_SVE_Pg4_5,
+ FLD_SVE_Pg4_10,
+ FLD_SVE_Pg4_16,
+ FLD_SVE_Pm,
+ FLD_SVE_Pn,
+ FLD_SVE_Pt,
+ FLD_SVE_Rm,
+ FLD_SVE_Rn,
+ FLD_SVE_Vd,
+ FLD_SVE_Vm,
+ FLD_SVE_Vn,
+ FLD_SVE_Za_5,
+ FLD_SVE_Za_16,
+ FLD_SVE_Zd,
+ FLD_SVE_Zm_5,
+ FLD_SVE_Zm_16,
+ FLD_SVE_Zn,
+ FLD_SVE_Zt,
+ FLD_SVE_i1,
+ FLD_SVE_i3h,
+ FLD_SVE_i3l,
+ FLD_SVE_i3h2,
+ FLD_SVE_i2h,
+ FLD_SVE_imm3,
+ FLD_SVE_imm4,
+ FLD_SVE_imm5,
+ FLD_SVE_imm5b,
+ FLD_SVE_imm6,
+ FLD_SVE_imm7,
+ FLD_SVE_imm8,
+ FLD_SVE_imm9,
+ FLD_SVE_immr,
+ FLD_SVE_imms,
+ FLD_SVE_msz,
+ FLD_SVE_pattern,
+ FLD_SVE_prfop,
+ FLD_SVE_rot1,
+ FLD_SVE_rot2,
+ FLD_SVE_rot3,
+ FLD_SVE_sz,
+ FLD_SVE_size,
+ FLD_SVE_sz2,
+ FLD_SVE_tsz,
+ FLD_SVE_tszh,
+ FLD_SVE_tszl_8,
+ FLD_SVE_tszl_19,
+ FLD_SVE_xs_14,
+ FLD_SVE_xs_22,
+ FLD_rotate1,
+ FLD_rotate2,
+ FLD_rotate3,
+ FLD_SM3_imm2,
+ FLD_sz
};
/* Field description. */
extern const aarch64_operand aarch64_operands[];
+enum err_type
+verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
+ bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
+
/* Operand flags. */
#define OPD_F_HAS_INSERTER 0x00000001
value by 2 to get the value
of an immediate operand. */
#define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
+#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
+#define OPD_F_OD_LSB 5
+#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
+#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
+ value by 4 to get the value
+ of an immediate operand. */
+
+
+/* Register flags. */
+
+#undef F_DEPRECATED
+#define F_DEPRECATED (1 << 0) /* Deprecated system register. */
+
+#undef F_ARCHEXT
+#define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
+
+#undef F_HASXT
+#define F_HASXT (1 << 2) /* System instruction register <Xt>
+ operand. */
+
+#undef F_REG_READ
+#define F_REG_READ (1 << 3) /* Register can only be used to read values
+ out of. */
+
+#undef F_REG_WRITE
+#define F_REG_WRITE (1 << 4) /* Register can only be written to but not
+ read from. */
+
+/* HINT operand flags. */
+#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
+
+/* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
+#define HINT_ENCODE(flag, val) ((flag << 8) | val)
+#define HINT_FLAG(val) (val >> 8)
+#define HINT_VAL(val) (val & 0xff)
static inline bfd_boolean
operand_has_inserter (const aarch64_operand *operand)
return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
}
+static inline bfd_boolean
+operand_need_shift_by_four (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+}
+
static inline bfd_boolean
operand_maybe_stack_pointer (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
}
+/* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
+static inline unsigned int
+get_operand_specific_data (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
+}
+
+/* Return the width of field number N of operand *OPERAND. */
+static inline unsigned
+get_operand_field_width (const aarch64_operand *operand, unsigned n)
+{
+ assert (operand->fields[n] != FLD_NIL);
+ return fields[operand->fields[n]].width;
+}
+
/* Return the total width of the operand *OPERAND. */
static inline unsigned
get_operand_fields_width (const aarch64_operand *operand)
{
return extract_field_2 (&fields[kind], code, mask);
}
+
+extern aarch64_insn
+extract_fields (aarch64_insn code, aarch64_insn mask, ...);
\f
/* Inline functions selecting operand to do the encoding/decoding for a
certain instruction bit-field. */
aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
-bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
+bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);
bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
int aarch64_shrink_expanded_imm8 (uint64_t);