/* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
- Copyright (C) 2012-2018 Free Software Foundation, Inc.
+ Copyright (C) 2012-2019 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
FLD_imm6_2,
FLD_imm4,
FLD_imm4_2,
+ FLD_imm4_3,
FLD_imm5,
FLD_imm7,
FLD_imm8,
FLD_SVE_Zt,
FLD_SVE_i1,
FLD_SVE_i3h,
+ FLD_SVE_i3l,
+ FLD_SVE_i3h2,
+ FLD_SVE_i2h,
FLD_SVE_imm3,
FLD_SVE_imm4,
FLD_SVE_imm5,
FLD_SVE_prfop,
FLD_SVE_rot1,
FLD_SVE_rot2,
+ FLD_SVE_rot3,
FLD_SVE_sz,
+ FLD_SVE_size,
+ FLD_SVE_sz2,
FLD_SVE_tsz,
FLD_SVE_tszh,
FLD_SVE_tszl_8,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
- FLD_SM3_imm2
+ FLD_SM3_imm2,
+ FLD_sz
};
/* Field description. */
#define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
#define OPD_F_OD_LSB 5
#define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
+#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
+ value by 4 to get the value
+ of an immediate operand. */
+
/* Register flags. */
#define F_REG_WRITE (1 << 4) /* Register can only be written to but not
read from. */
+/* HINT operand flags. */
+#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
+
+/* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
+#define HINT_ENCODE(flag, val) ((flag << 8) | val)
+#define HINT_FLAG(val) (val >> 8)
+#define HINT_VAL(val) (val & 0xff)
+
static inline bfd_boolean
operand_has_inserter (const aarch64_operand *operand)
{
return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
}
+static inline bfd_boolean
+operand_need_shift_by_four (const aarch64_operand *operand)
+{
+ return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
+}
+
static inline bfd_boolean
operand_maybe_stack_pointer (const aarch64_operand *operand)
{