/* Instruction printing code for the ARC.
- Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005
- Free Software Foundation, Inc.
- Contributed by Doug Evans (dje@cygnus.com).
+ Copyright (C) 1994-2016 Free Software Foundation, Inc.
- This program is free software; you can redistribute it and/or modify
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
+ the Free Software Foundation; either version 3, or (at your option)
+ any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
MA 02110-1301, USA. */
-#include "ansidecl.h"
-#include "libiberty.h"
+#include "sysdep.h"
+#include <stdio.h>
+#include <assert.h>
#include "dis-asm.h"
#include "opcode/arc.h"
-#include "elf-bfd.h"
#include "elf/arc.h"
-#include <string.h>
-#include "opintl.h"
-
-#include <stdarg.h>
#include "arc-dis.h"
#include "arc-ext.h"
+#include "elf-bfd.h"
+#include "libiberty.h"
+#include "opintl.h"
-#ifndef dbg
-#define dbg (0)
-#endif
+/* Structure used to iterate over, and extract the values for, operands of
+ an opcode. */
-/* Classification of the opcodes for the decoder to print
- the instructions. */
+struct arc_operand_iterator
+{
+ enum
+ {
+ OPERAND_ITERATOR_STANDARD,
+ OPERAND_ITERATOR_LONG
+ } mode;
+
+ /* The array of 32-bit values that make up this instruction. All
+ required values have been pre-loaded into this array during the
+ find_format call. */
+ unsigned *insn;
+
+ union
+ {
+ struct
+ {
+ /* The opcode this iterator is operating on. */
+ const struct arc_opcode *opcode;
-typedef enum
+ /* The index into the opcodes operand index list. */
+ const unsigned char *opidx;
+ } standard;
+
+ struct
+ {
+ /* The long instruction opcode this iterator is operating on. */
+ const struct arc_long_opcode *long_opcode;
+
+ /* Two indexes into the opcodes operand index lists. */
+ const unsigned char *opidx_base, *opidx_limm;
+ } long_insn;
+ } state;
+};
+
+/* Globals variables. */
+
+static const char * const regnames[64] =
{
- CLASS_A4_ARITH,
- CLASS_A4_OP3_GENERAL,
- CLASS_A4_FLAG,
- /* All branches other than JC. */
- CLASS_A4_BRANCH,
- CLASS_A4_JC ,
- /* All loads other than immediate
- indexed loads. */
- CLASS_A4_LD0,
- CLASS_A4_LD1,
- CLASS_A4_ST,
- CLASS_A4_SR,
- /* All single operand instructions. */
- CLASS_A4_OP3_SUBOPC3F,
- CLASS_A4_LR
-} a4_decoding_class;
-
-#define BIT(word,n) ((word) & (1 << n))
-#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
-#define OPCODE(word) (BITS ((word), 27, 31))
-#define FIELDA(word) (BITS ((word), 21, 26))
-#define FIELDB(word) (BITS ((word), 15, 20))
-#define FIELDC(word) (BITS ((word), 9, 14))
-
-/* FIELD D is signed in all of its uses, so we make sure argument is
- treated as signed for bit shifting purposes: */
-#define FIELDD(word) (BITS (((signed int)word), 0, 8))
-
-#define PUT_NEXT_WORD_IN(a) \
- do \
- { \
- if (is_limm == 1 && !NEXT_WORD (1)) \
- mwerror (state, _("Illegal limm reference in last instruction!\n")); \
- a = state->words[1]; \
- } \
- while (0)
-
-#define CHECK_FLAG_COND_NULLIFY() \
- do \
- { \
- if (is_shimm == 0) \
- { \
- flag = BIT (state->words[0], 8); \
- state->nullifyMode = BITS (state->words[0], 5, 6); \
- cond = BITS (state->words[0], 0, 4); \
- } \
- } \
- while (0)
-
-#define CHECK_COND() \
- do \
- { \
- if (is_shimm == 0) \
- cond = BITS (state->words[0], 0, 4); \
- } \
- while (0)
-
-#define CHECK_FIELD(field) \
- do \
- { \
- if (field == 62) \
- { \
- is_limm++; \
- field##isReg = 0; \
- PUT_NEXT_WORD_IN (field); \
- limm_value = field; \
- } \
- else if (field > 60) \
- { \
- field##isReg = 0; \
- is_shimm++; \
- flag = (field == 61); \
- field = FIELDD (state->words[0]); \
- } \
- } \
- while (0)
-
-#define CHECK_FIELD_A() \
- do \
- { \
- fieldA = FIELDA (state->words[0]); \
- if (fieldA > 60) \
- { \
- fieldAisReg = 0; \
- fieldA = 0; \
- } \
- } \
- while (0)
-
-#define CHECK_FIELD_B() \
- do \
- { \
- fieldB = FIELDB (state->words[0]); \
- CHECK_FIELD (fieldB); \
- } \
- while (0)
-
-#define CHECK_FIELD_C() \
- do \
- { \
- fieldC = FIELDC (state->words[0]); \
- CHECK_FIELD (fieldC); \
- } \
- while (0)
-
-#define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
-#define IS_REG(x) (field##x##isReg)
-#define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT (x, "[","]","","")
-#define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT (x, "",",[","",",[")
-#define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT (x, ",","]",",","]")
-#define WRITE_FORMAT_x_RB(x) WRITE_FORMAT (x, "","]","","]")
-#define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT (x, ",","",",","")
-#define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT (x, "",",","",",")
-#define WRITE_FORMAT_x(x) WRITE_FORMAT (x, "","","","")
-#define WRITE_FORMAT(x,cb1,ca1,cb,ca) strcat (formatString, \
- (IS_REG (x) ? cb1"%r"ca1 : \
- usesAuxReg ? cb"%a"ca : \
- IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
-#define WRITE_FORMAT_RB() strcat (formatString, "]")
-#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
-#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
-
-#define NEXT_WORD(x) (offset += 4, state->words[x])
-
-#define add_target(x) (state->targets[state->tcnt++] = (x))
-
-static char comment_prefix[] = "\t; ";
+ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+ "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+ "r24", "r25", "gp", "fp", "sp", "ilink", "r30", "blink",
+
+ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
+ "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
+ "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
+ "r56", "r57", "ACCL", "ACCH", "lp_count", "rezerved", "LIMM", "pcl"
+};
-static const char *
-core_reg_name (struct arcDisState * state, int val)
+/* This structure keeps track which instruction class(es)
+ should be ignored durring disassembling. */
+
+typedef struct skipclass
{
- if (state->coreRegName)
- return (*state->coreRegName)(state->_this, val);
- return 0;
-}
+ insn_class_t insn_class;
+ insn_subclass_t subclass;
+ struct skipclass *nxt;
+} skipclass_t, *linkclass;
-static const char *
-aux_reg_name (struct arcDisState * state, int val)
+/* Intial classes of instructions to be consider first when
+ disassembling. */
+static linkclass decodelist = NULL;
+
+/* Macros section. */
+
+#ifdef DEBUG
+# define pr_debug(fmt, args...) fprintf (stderr, fmt, ##args)
+#else
+# define pr_debug(fmt, args...)
+#endif
+
+#define ARRANGE_ENDIAN(info, buf) \
+ (info->endian == BFD_ENDIAN_LITTLE ? bfd_getm32 (bfd_getl32 (buf)) \
+ : bfd_getb32 (buf))
+
+#define BITS(word,s,e) (((word) << (sizeof (word) * 8 - 1 - e)) >> \
+ (s + (sizeof (word) * 8 - 1 - e)))
+#define OPCODE(word) (BITS ((word), 27, 31))
+
+#define OPCODE_AC(word) (BITS ((word), 11, 15))
+
+/* Functions implementation. */
+
+/* Return TRUE when two classes are not opcode conflicting. */
+
+static bfd_boolean
+is_compatible_p (insn_class_t classA,
+ insn_subclass_t sclassA,
+ insn_class_t classB,
+ insn_subclass_t sclassB)
{
- if (state->auxRegName)
- return (*state->auxRegName)(state->_this, val);
- return 0;
+ if (classA == DSP && sclassB == DPX)
+ return FALSE;
+ if (sclassA == DPX && classB == DSP)
+ return FALSE;
+ return TRUE;
}
-static const char *
-cond_code_name (struct arcDisState * state, int val)
+/* Add a new element to the decode list. */
+
+static void
+add_to_decodelist (insn_class_t insn_class,
+ insn_subclass_t subclass)
{
- if (state->condCodeName)
- return (*state->condCodeName)(state->_this, val);
- return 0;
+ linkclass t = (linkclass) xmalloc (sizeof (skipclass_t));
+
+ t->insn_class = insn_class;
+ t->subclass = subclass;
+ t->nxt = decodelist;
+ decodelist = t;
}
-static const char *
-instruction_name (struct arcDisState * state,
- int op1,
- int op2,
- int * flags)
+/* Return TRUE if we need to skip the opcode from being
+ disassembled. */
+
+static bfd_boolean
+skip_this_opcode (const struct arc_opcode * opcode,
+ struct disassemble_info * info)
{
- if (state->instName)
- return (*state->instName)(state->_this, op1, op2, flags);
- return 0;
+ linkclass t = decodelist;
+ bfd_boolean addme = TRUE;
+
+ /* Check opcode for major 0x06, return if it is not in. */
+ if (OPCODE (opcode->opcode) != 0x06)
+ return FALSE;
+
+ while (t != NULL
+ && is_compatible_p (t->insn_class, t->subclass,
+ opcode->insn_class, opcode->subclass))
+ {
+ if ((t->insn_class == opcode->insn_class)
+ && (t->subclass == opcode->subclass))
+ addme = FALSE;
+ t = t->nxt;
+ }
+
+ /* If we found an incompatibility then we must skip. */
+ if (t != NULL)
+ return TRUE;
+
+ /* Even if we do not precisely know the if the right mnemonics
+ is correctly displayed, keep the disassmbled code class
+ consistent. */
+ if (addme)
+ {
+ switch (opcode->insn_class)
+ {
+ case DSP:
+ case FLOAT:
+ /* Add to the conflict list only the classes which
+ counts. */
+ add_to_decodelist (opcode->insn_class, opcode->subclass);
+ /* Warn if we have to decode an opcode and no preferred
+ classes have been chosen. */
+ info->fprintf_func (info->stream, _("\n\
+Warning: disassembly may be wrong due to guessed opcode class choice.\n\
+ Use -M<class[,class]> to select the correct opcode class(es).\n\t\t\t\t"));
+ break;
+ default:
+ break;
+ }
+ }
+ return FALSE;
}
-static void
-mwerror (struct arcDisState * state, const char * msg)
+static bfd_vma
+bfd_getm32 (unsigned int data)
{
- if (state->err != 0)
- (*state->err)(state->_this, (msg));
+ bfd_vma value = 0;
+
+ value = ((data & 0xff00) | (data & 0xff)) << 16;
+ value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
+ return value;
}
-static const char *
-post_address (struct arcDisState * state, int addr)
+static bfd_boolean
+special_flag_p (const char *opname,
+ const char *flgname)
{
- static char id[3 * ARRAY_SIZE (state->addresses)];
- int j, i = state->acnt;
+ const struct arc_flag_special *flg_spec;
+ unsigned i, j, flgidx;
- if (i < ((int) ARRAY_SIZE (state->addresses)))
+ for (i = 0; i < arc_num_flag_special; i++)
{
- state->addresses[i] = addr;
- ++state->acnt;
- j = i*3;
- id[j+0] = '@';
- id[j+1] = '0'+i;
- id[j+2] = 0;
-
- return id + j;
+ flg_spec = &arc_flag_special_cases[i];
+
+ if (strcmp (opname, flg_spec->name))
+ continue;
+
+ /* Found potential special case instruction. */
+ for (j=0;; ++j)
+ {
+ flgidx = flg_spec->flags[j];
+ if (flgidx == 0)
+ break; /* End of the array. */
+
+ if (strcmp (flgname, arc_flag_operands[flgidx].name) == 0)
+ return TRUE;
+ }
}
- return "";
+ return FALSE;
}
-static void
-arc_sprintf (struct arcDisState *state, char *buf, const char *format, ...)
+/* Find opcode from ARC_TABLE given the instruction described by INSN and
+ INSNLEN. The ISA_MASK restricts the possible matches in ARC_TABLE. */
+
+static const struct arc_opcode *
+find_format_from_table (struct disassemble_info *info,
+ const struct arc_opcode *arc_table,
+ unsigned *insn,
+ unsigned int insn_len,
+ unsigned isa_mask,
+ bfd_boolean *has_limm,
+ bfd_boolean overlaps)
{
- char *bp;
- const char *p;
- int size, leading_zero, regMap[2];
- long auxNum;
- va_list ap;
-
- va_start (ap, format);
-
- bp = buf;
- *bp = 0;
- p = format;
- auxNum = -1;
- regMap[0] = 0;
- regMap[1] = 0;
-
- while (1)
- switch (*p++)
- {
- case 0:
- goto DOCOMM; /* (return) */
- default:
- *bp++ = p[-1];
- break;
- case '%':
- size = 0;
- leading_zero = 0;
- RETRY: ;
- switch (*p++)
- {
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
+ unsigned int i = 0;
+ const struct arc_opcode *opcode = NULL;
+ const unsigned char *opidx;
+ const unsigned char *flgidx;
+
+ do
+ {
+ bfd_boolean invalid = FALSE;
+
+ opcode = &arc_table[i++];
+
+ if (ARC_SHORT (opcode->mask) && (insn_len == 2))
+ {
+ if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
+ continue;
+ }
+ else if (!ARC_SHORT (opcode->mask) && (insn_len == 4))
+ {
+ if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
+ continue;
+ }
+ else
+ continue;
+
+ if ((insn[0] ^ opcode->opcode) & opcode->mask)
+ continue;
+
+ if (!(opcode->cpu & isa_mask))
+ continue;
+
+ *has_limm = FALSE;
+
+ /* Possible candidate, check the operands. */
+ for (opidx = opcode->operands; *opidx; opidx++)
+ {
+ int value;
+ const struct arc_operand *operand = &arc_operands[*opidx];
+
+ if (operand->flags & ARC_OPERAND_FAKE)
+ continue;
+
+ if (operand->extract)
+ value = (*operand->extract) (insn[0], &invalid);
+ else
+ value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+
+ /* Check for LIMM indicator. If it is there, then make sure
+ we pick the right format. */
+ if (operand->flags & ARC_OPERAND_IR
+ && !(operand->flags & ARC_OPERAND_LIMM))
{
- /* size. */
- size = p[-1] - '0';
- if (size == 0)
- leading_zero = 1; /* e.g. %08x */
- while (*p >= '0' && *p <= '9')
+ if ((value == 0x3E && insn_len == 4)
+ || (value == 0x1E && insn_len == 2))
{
- size = size * 10 + *p - '0';
- p++;
+ invalid = TRUE;
+ break;
}
- goto RETRY;
}
-#define inc_bp() bp = bp + strlen (bp)
- case 'h':
- {
- unsigned u = va_arg (ap, int);
+ if (operand->flags & ARC_OPERAND_LIMM
+ && !(operand->flags & ARC_OPERAND_DUPLICATE))
+ *has_limm = TRUE;
+ }
- /* Hex. We can change the format to 0x%08x in
- one place, here, if we wish.
- We add underscores for easy reading. */
- if (u > 65536)
- sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
- else
- sprintf (bp, "0x%x", u);
- inc_bp ();
- }
- break;
- case 'X': case 'x':
+ /* Check the flags. */
+ for (flgidx = opcode->flags; *flgidx; flgidx++)
+ {
+ /* Get a valid flag class. */
+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+ const unsigned *flgopridx;
+ int foundA = 0, foundB = 0;
+ unsigned int value;
+
+ /* Check first the extensions. */
+ if (cl_flags->flag_class & F_CLASS_EXTEND)
{
- int val = va_arg (ap, int);
-
- if (size != 0)
- if (leading_zero)
- sprintf (bp, "%0*x", size, val);
- else
- sprintf (bp, "%*x", size, val);
- else
- sprintf (bp, "%x", val);
- inc_bp ();
+ value = (insn[0] & 0x1F);
+ if (arcExtMap_condCodeName (value))
+ continue;
}
- break;
- case 'd':
- {
- int val = va_arg (ap, int);
- if (size != 0)
- sprintf (bp, "%*d", size, val);
- else
- sprintf (bp, "%d", val);
- inc_bp ();
+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
+ {
+ const struct arc_flag_operand *flg_operand =
+ &arc_flag_operands[*flgopridx];
+
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
+ if (value == flg_operand->code)
+ foundA = 1;
+ if (value)
+ foundB = 1;
}
- break;
- case 'r':
+
+ if (!foundA && foundB)
{
- /* Register. */
- int val = va_arg (ap, int);
+ invalid = TRUE;
+ break;
+ }
+ }
-#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
- regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
+ if (invalid)
+ continue;
- switch (val)
- {
- REG2NAME (26, "gp");
- REG2NAME (27, "fp");
- REG2NAME (28, "sp");
- REG2NAME (29, "ilink1");
- REG2NAME (30, "ilink2");
- REG2NAME (31, "blink");
- REG2NAME (60, "lp_count");
- default:
- {
- const char * ext;
-
- ext = core_reg_name (state, val);
- if (ext)
- sprintf (bp, "%s", ext);
- else
- sprintf (bp,"r%d",val);
- }
- break;
- }
- inc_bp ();
- } break;
+ if (insn_len == 4
+ && overlaps
+ && skip_this_opcode (opcode, info))
+ continue;
- case 'a':
- {
- /* Aux Register. */
- int val = va_arg (ap, int);
+ /* The instruction is valid. */
+ return opcode;
+ }
+ while (opcode->mask);
-#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
+ return NULL;
+}
- switch (val)
- {
- AUXREG2NAME (0x0, "status");
- AUXREG2NAME (0x1, "semaphore");
- AUXREG2NAME (0x2, "lp_start");
- AUXREG2NAME (0x3, "lp_end");
- AUXREG2NAME (0x4, "identity");
- AUXREG2NAME (0x5, "debug");
- default:
- {
- const char *ext;
-
- ext = aux_reg_name (state, val);
- if (ext)
- sprintf (bp, "%s", ext);
- else
- arc_sprintf (state, bp, "%h", val);
- }
- break;
- }
- inc_bp ();
- }
- break;
+/* Find long instructions matching values in INSN array. */
- case 's':
- {
- sprintf (bp, "%s", va_arg (ap, char *));
- inc_bp ();
- }
- break;
+static const struct arc_long_opcode *
+find_format_long_instructions (unsigned *insn,
+ unsigned int *insn_len,
+ unsigned isa_mask,
+ bfd_vma memaddr,
+ struct disassemble_info *info)
+{
+ unsigned int i;
+ unsigned limm = 0;
+ bfd_boolean limm_loaded = FALSE;
+
+ for (i = 0; i < arc_num_long_opcodes; ++i)
+ {
+ bfd_byte buffer[4];
+ int status;
+ const struct arc_opcode *opcode;
+
+ opcode = &arc_long_opcodes[i].base_opcode;
+
+ if (ARC_SHORT (opcode->mask) && (*insn_len == 2))
+ {
+ if (OPCODE_AC (opcode->opcode) != OPCODE_AC (insn[0]))
+ continue;
+ }
+ else if (!ARC_SHORT (opcode->mask) && (*insn_len == 4))
+ {
+ if (OPCODE (opcode->opcode) != OPCODE (insn[0]))
+ continue;
+ }
+ else
+ continue;
+
+ if ((insn[0] ^ opcode->opcode) & opcode->mask)
+ continue;
+
+ if (!(opcode->cpu & isa_mask))
+ continue;
+
+ if (!limm_loaded)
+ {
+ status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
+ 4, info);
+ if (status != 0)
+ return NULL;
+
+ limm = ARRANGE_ENDIAN (info, buffer);
+ limm_loaded = TRUE;
+ }
+
+ /* Check the second word using the mask and template. */
+ if ((limm & arc_long_opcodes[i].limm_mask)
+ != arc_long_opcodes[i].limm_template)
+ continue;
+
+ (*insn_len) += 4;
+ insn[1] = limm;
+ return &arc_long_opcodes[i];
+ }
+
+ return NULL;
+}
+
+/* Find opcode for INSN, trying various different sources. The instruction
+ length in INSN_LEN will be updated if the instruction requires a LIMM
+ extension, and the additional values loaded into the INSN array (which
+ must be big enough).
+
+ A pointer to the opcode is placed into OPCODE_RESULT, and ITER is
+ initialised, ready to iterate over the operands of the found opcode.
+
+ This function returns TRUE in almost all cases, FALSE is reserved to
+ indicate an error (failing to find an opcode is not an error) a
+ returned result of FALSE would indicate that the disassembler can't
+ continue.
+
+ If no matching opcode is found then the returned result will be TRUE,
+ the value placed into OPCODE_RESULT will be NULL, ITER will be
+ undefined, and INSN_LEN will be unchanged.
+
+ If a matching opcode is found, then the returned result will be TRUE,
+ the opcode pointer is placed into OPCODE_RESULT, INSN_LEN will be
+ increased by 4 if the instruction requires a LIMM, and the LIMM value
+ will have been loaded into the INSN[1]. Finally, ITER will have been
+ initialised so that calls to OPERAND_ITERATOR_NEXT will iterate over
+ the opcode's operands. */
+
+static bfd_boolean
+find_format (bfd_vma memaddr,
+ unsigned * insn,
+ unsigned int * insn_len,
+ unsigned isa_mask,
+ struct disassemble_info * info,
+ const struct arc_opcode ** opcode_result,
+ struct arc_operand_iterator * iter)
+{
+ const struct arc_opcode *opcode = NULL;
+ bfd_boolean needs_limm;
+ const extInstruction_t *einsn;
+
+ /* First, try the extension instructions. */
+ einsn = arcExtMap_insn (OPCODE (insn[0]), insn[0]);
+ if (einsn != NULL)
+ {
+ const char *errmsg = NULL;
+
+ opcode = arcExtMap_genOpcode (einsn, isa_mask, &errmsg);
+ if (opcode == NULL)
+ {
+ (*info->fprintf_func) (info->stream, "\
+An error occured while generating the extension instruction operations");
+ *opcode_result = NULL;
+ return FALSE;
+ }
+
+ opcode = find_format_from_table (info, opcode, insn, *insn_len,
+ isa_mask, &needs_limm, FALSE);
+ }
- default:
- fprintf (stderr, "?? format %c\n", p[-1]);
- break;
- }
- }
+ /* Then, try finding the first match in the opcode table. */
+ if (opcode == NULL)
+ opcode = find_format_from_table (info, arc_opcodes, insn, *insn_len,
+ isa_mask, &needs_limm, TRUE);
- DOCOMM: *bp = 0;
- va_end (ap);
+ if (needs_limm && opcode != NULL)
+ {
+ bfd_byte buffer[4];
+ int status;
+
+ status = (*info->read_memory_func) (memaddr + *insn_len, buffer,
+ 4, info);
+ if (status != 0)
+ {
+ opcode = NULL;
+ }
+ else
+ {
+ insn[1] = ARRANGE_ENDIAN (info, buffer);
+ *insn_len += 4;
+ }
+ }
+
+ if (opcode == NULL)
+ {
+ const struct arc_long_opcode *long_opcode;
+
+ /* No instruction found yet, try the long instructions. */
+ long_opcode =
+ find_format_long_instructions (insn, insn_len, isa_mask,
+ memaddr, info);
+
+ if (long_opcode != NULL)
+ {
+ iter->mode = OPERAND_ITERATOR_LONG;
+ iter->insn = insn;
+ iter->state.long_insn.long_opcode = long_opcode;
+ iter->state.long_insn.opidx_base =
+ long_opcode->base_opcode.operands;
+ iter->state.long_insn.opidx_limm =
+ long_opcode->operands;
+ opcode = &long_opcode->base_opcode;
+ }
+ }
+ else
+ {
+ iter->mode = OPERAND_ITERATOR_STANDARD;
+ iter->insn = insn;
+ iter->state.standard.opcode = opcode;
+ iter->state.standard.opidx = opcode->operands;
+ }
+
+ *opcode_result = opcode;
+ return TRUE;
}
static void
-write_comments_(struct arcDisState * state,
- int shimm,
- int is_limm,
- long limm_value)
+print_flags (const struct arc_opcode *opcode,
+ unsigned *insn,
+ struct disassemble_info *info)
{
- if (state->commentBuffer != 0)
+ const unsigned char *flgidx;
+ unsigned int value;
+
+ /* Now extract and print the flags. */
+ for (flgidx = opcode->flags; *flgidx; flgidx++)
{
- int i;
+ /* Get a valid flag class. */
+ const struct arc_flag_class *cl_flags = &arc_flag_classes[*flgidx];
+ const unsigned *flgopridx;
- if (is_limm)
+ /* Check first the extensions. */
+ if (cl_flags->flag_class & F_CLASS_EXTEND)
{
- const char *name = post_address (state, limm_value + shimm);
+ const char *name;
+ value = (insn[0] & 0x1F);
- if (*name != 0)
- WRITE_COMMENT (name);
+ name = arcExtMap_condCodeName (value);
+ if (name)
+ {
+ (*info->fprintf_func) (info->stream, ".%s", name);
+ continue;
+ }
}
- for (i = 0; i < state->commNum; i++)
+
+ for (flgopridx = cl_flags->flags; *flgopridx; ++flgopridx)
{
- if (i == 0)
- strcpy (state->commentBuffer, comment_prefix);
- else
- strcat (state->commentBuffer, ", ");
- strncat (state->commentBuffer, state->comm[i],
- sizeof (state->commentBuffer));
+ const struct arc_flag_operand *flg_operand =
+ &arc_flag_operands[*flgopridx];
+
+ if (!flg_operand->favail)
+ continue;
+
+ value = (insn[0] >> flg_operand->shift)
+ & ((1 << flg_operand->bits) - 1);
+ if (value == flg_operand->code)
+ {
+ /* FIXME!: print correctly nt/t flag. */
+ if (!special_flag_p (opcode->name, flg_operand->name))
+ (*info->fprintf_func) (info->stream, ".");
+ else if (info->insn_type == dis_dref)
+ {
+ switch (flg_operand->name[0])
+ {
+ case 'b':
+ info->data_size = 1;
+ break;
+ case 'h':
+ case 'w':
+ info->data_size = 2;
+ break;
+ default:
+ info->data_size = 4;
+ break;
+ }
+ }
+ if (flg_operand->name[0] == 'd'
+ && flg_operand->name[1] == 0)
+ info->branch_delay_insns = 1;
+
+ /* Check if it is a conditional flag. */
+ if (cl_flags->flag_class & F_CLASS_COND)
+ {
+ if (info->insn_type == dis_jsr)
+ info->insn_type = dis_condjsr;
+ else if (info->insn_type == dis_branch)
+ info->insn_type = dis_condbranch;
+ }
+
+ (*info->fprintf_func) (info->stream, "%s", flg_operand->name);
+ }
}
}
}
-#define write_comments2(x) write_comments_ (state, x, is_limm, limm_value)
-#define write_comments() write_comments2 (0)
-
-static const char *condName[] =
+static const char *
+get_auxreg (const struct arc_opcode *opcode,
+ int value,
+ unsigned isa_mask)
{
- /* 0..15. */
- "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
- "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
-};
+ const char *name;
+ unsigned int i;
+ const struct arc_aux_reg *auxr = &arc_aux_regs[0];
-static void
-write_instr_name_(struct arcDisState * state,
- const char * instrName,
- int cond,
- int condCodeIsPartOfName,
- int flag,
- int signExtend,
- int addrWriteBack,
- int directMem)
-{
- strcpy (state->instrBuffer, instrName);
+ if (opcode->insn_class != AUXREG)
+ return NULL;
+
+ name = arcExtMap_auxRegName (value);
+ if (name)
+ return name;
- if (cond > 0)
+ for (i = 0; i < arc_num_aux_regs; i++, auxr++)
{
- const char *cc = 0;
+ if (!(auxr->cpu & isa_mask))
+ continue;
- if (!condCodeIsPartOfName)
- strcat (state->instrBuffer, ".");
+ if (auxr->subclass != NONE)
+ return NULL;
- if (cond < 16)
- cc = condName[cond];
- else
- cc = cond_code_name (state, cond);
+ if (auxr->address == value)
+ return auxr->name;
+ }
+ return NULL;
+}
- if (!cc)
- cc = "???";
+/* Calculate the instruction length for an instruction starting with MSB
+ and LSB, the most and least significant byte. The ISA_MASK is used to
+ filter the instructions considered to only those that are part of the
+ current architecture.
- strcat (state->instrBuffer, cc);
- }
+ The instruction lengths are calculated from the ARC_OPCODE table, and
+ cached for later use. */
- if (flag)
- strcat (state->instrBuffer, ".f");
+static unsigned int
+arc_insn_length (bfd_byte msb, bfd_byte lsb, struct disassemble_info *info)
+{
+ bfd_byte major_opcode = msb >> 3;
- switch (state->nullifyMode)
+ switch (info->mach)
{
- case BR_exec_always:
- strcat (state->instrBuffer, ".d");
+ case bfd_mach_arc_arc700:
+ /* The nps400 extension set requires this special casing of the
+ instruction length calculation. Right now this is not causing any
+ problems as none of the known extensions overlap in opcode space,
+ but, if they ever do then we might need to start carrying
+ information around in the elf about which extensions are in use. */
+ if (major_opcode == 0xb)
+ {
+ bfd_byte minor_opcode = lsb & 0x1f;
+
+ if (minor_opcode < 4)
+ return 2;
+ }
+ case bfd_mach_arc_arc600:
+ return (major_opcode > 0xb) ? 2 : 4;
break;
- case BR_exec_when_jump:
- strcat (state->instrBuffer, ".jd");
+
+ case bfd_mach_arc_arcv2:
+ return (major_opcode > 0x7) ? 2 : 4;
break;
+
+ default:
+ abort ();
}
+}
- if (signExtend)
- strcat (state->instrBuffer, ".x");
+/* Extract and return the value of OPERAND from the instruction whose value
+ is held in the array INSN. */
- if (addrWriteBack)
- strcat (state->instrBuffer, ".a");
+static int
+extract_operand_value (const struct arc_operand *operand, unsigned *insn)
+{
+ int value;
- if (directMem)
- strcat (state->instrBuffer, ".di");
+ /* Read the limm operand, if required. */
+ if (operand->flags & ARC_OPERAND_LIMM)
+ /* The second part of the instruction value will have been loaded as
+ part of the find_format call made earlier. */
+ value = insn[1];
+ else
+ {
+ if (operand->extract)
+ value = (*operand->extract) (insn[0], (int *) NULL);
+ else
+ {
+ if (operand->flags & ARC_OPERAND_ALIGNED32)
+ {
+ value = (insn[0] >> operand->shift)
+ & ((1 << (operand->bits - 2)) - 1);
+ value = value << 2;
+ }
+ else
+ {
+ value = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ }
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ {
+ int signbit = 1 << (operand->bits - 1);
+ value = (value ^ signbit) - signbit;
+ }
+ }
+ }
+
+ return value;
}
-#define write_instr_name() \
- do \
- { \
- write_instr_name_(state, instrName,cond, condCodeIsPartOfName, \
- flag, signExtend, addrWriteBack, directMem); \
- formatString[0] = '\0'; \
- } \
- while (0)
+/* Find the next operand, and the operands value from ITER. Return TRUE if
+ there is another operand, otherwise return FALSE. If there is an
+ operand returned then the operand is placed into OPERAND, and the value
+ into VALUE. If there is no operand returned then OPERAND and VALUE are
+ unchanged. */
-enum
+static bfd_boolean
+operand_iterator_next (struct arc_operand_iterator *iter,
+ const struct arc_operand **operand,
+ int *value)
{
- op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
- op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
- op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
- op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
-};
+ if (iter->mode == OPERAND_ITERATOR_STANDARD)
+ {
+ if (*iter->state.standard.opidx == 0)
+ {
+ *operand = NULL;
+ return FALSE;
+ }
+
+ *operand = &arc_operands[*iter->state.standard.opidx];
+ *value = extract_operand_value (*operand, iter->insn);
+ iter->state.standard.opidx++;
+ }
+ else
+ {
+ const struct arc_operand *operand_base, *operand_limm;
+ int value_base, value_limm;
+
+ if (*iter->state.long_insn.opidx_limm == 0)
+ {
+ *operand = NULL;
+ return FALSE;
+ }
+
+ operand_base = &arc_operands[*iter->state.long_insn.opidx_base];
+ operand_limm = &arc_operands[*iter->state.long_insn.opidx_limm];
+
+ if (operand_base->flags & ARC_OPERAND_LIMM)
+ {
+ /* We've reached the end of the operand list. */
+ *operand = NULL;
+ return FALSE;
+ }
+
+ value_base = value_limm = 0;
+ if (!(operand_limm->flags & ARC_OPERAND_IGNORE))
+ {
+ /* This should never happen. If it does then the use of
+ extract_operand_value below will access memory beyond
+ the insn array. */
+ assert ((operand_limm->flags & ARC_OPERAND_LIMM) == 0);
+
+ *operand = operand_limm;
+ value_limm = extract_operand_value (*operand, &iter->insn[1]);
+ }
+
+ if (!(operand_base->flags & ARC_OPERAND_IGNORE))
+ {
+ *operand = operand_base;
+ value_base = extract_operand_value (*operand, iter->insn);
+ }
+
+ /* This is a bit of a fudge. There's no reason why simply ORing
+ together the two values is the right thing to do, however, for all
+ the cases we currently have, it is the right thing, so, for now,
+ I've put off solving the more complex problem. */
+ *value = value_base | value_limm;
+
+ iter->state.long_insn.opidx_base++;
+ iter->state.long_insn.opidx_limm++;
+ }
+ return TRUE;
+}
-extern disassemble_info tm_print_insn_info;
+/* Helper for parsing the options. */
-static int
-dsmOneArcInst (bfd_vma addr, struct arcDisState * state)
+static void
+parse_option (char *option)
{
- int condCodeIsPartOfName = 0;
- a4_decoding_class decodingClass;
- const char * instrName;
- int repeatsOp = 0;
- int fieldAisReg = 1;
- int fieldBisReg = 1;
- int fieldCisReg = 1;
- int fieldA;
- int fieldB;
- int fieldC = 0;
- int flag = 0;
- int cond = 0;
- int is_shimm = 0;
- int is_limm = 0;
- long limm_value = 0;
- int signExtend = 0;
- int addrWriteBack = 0;
- int directMem = 0;
- int is_linked = 0;
- int offset = 0;
- int usesAuxReg = 0;
- int flags;
- int ignoreFirstOpd;
- char formatString[60];
-
- state->instructionLen = 4;
- state->nullifyMode = BR_exec_when_no_jump;
- state->opWidth = 12;
- state->isBranch = 0;
-
- state->_mem_load = 0;
- state->_ea_present = 0;
- state->_load_len = 0;
- state->ea_reg1 = no_reg;
- state->ea_reg2 = no_reg;
- state->_offset = 0;
-
- if (! NEXT_WORD (0))
- return 0;
-
- state->_opcode = OPCODE (state->words[0]);
- instrName = 0;
- decodingClass = CLASS_A4_ARITH; /* default! */
- repeatsOp = 0;
- condCodeIsPartOfName=0;
- state->commNum = 0;
- state->tcnt = 0;
- state->acnt = 0;
- state->flow = noflow;
- ignoreFirstOpd = 0;
-
- if (state->commentBuffer)
- state->commentBuffer[0] = '\0';
-
- switch (state->_opcode)
+ if (CONST_STRNEQ (option, "dsp"))
+ add_to_decodelist (DSP, NONE);
+
+ else if (CONST_STRNEQ (option, "spfp"))
+ add_to_decodelist (FLOAT, SPX);
+
+ else if (CONST_STRNEQ (option, "dpfp"))
+ add_to_decodelist (FLOAT, DPX);
+
+ else if (CONST_STRNEQ (option, "quarkse_em"))
+ add_to_decodelist (FLOAT, QUARKSE);
+
+ else if (CONST_STRNEQ (option, "fpuda"))
+ add_to_decodelist (FLOAT, DPA);
+
+ else if (CONST_STRNEQ (option, "fpud"))
+ {
+ add_to_decodelist (FLOAT, SP);
+ add_to_decodelist (FLOAT, CVT);
+ }
+
+ else if (CONST_STRNEQ (option, "fpus"))
{
- case op_LD0:
- switch (BITS (state->words[0],1,2))
+ add_to_decodelist (FLOAT, DP);
+ add_to_decodelist (FLOAT, CVT);
+ }
+ else
+ fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
+}
+
+/* Go over the options list and parse it. */
+
+static void
+parse_disassembler_options (char *options)
+{
+ if (options == NULL)
+ return;
+
+ while (*options)
+ {
+ /* Skip empty options. */
+ if (*options == ',')
{
- case 0:
- instrName = "ld";
- state->_load_len = 4;
- break;
- case 1:
- instrName = "ldb";
- state->_load_len = 1;
- break;
- case 2:
- instrName = "ldw";
- state->_load_len = 2;
- break;
- default:
- instrName = "??? (0[3])";
- state->flow = invalid_instr;
- break;
+ ++ options;
+ continue;
}
- decodingClass = CLASS_A4_LD0;
+
+ parse_option (options);
+
+ while (*options != ',' && *options != '\0')
+ ++ options;
+ }
+}
+
+/* Disassemble ARC instructions. */
+
+static int
+print_insn_arc (bfd_vma memaddr,
+ struct disassemble_info *info)
+{
+ bfd_byte buffer[4];
+ unsigned int lowbyte, highbyte;
+ int status;
+ unsigned int insn_len;
+ unsigned insn[2] = { 0, 0 };
+ unsigned isa_mask;
+ const struct arc_opcode *opcode;
+ bfd_boolean need_comma;
+ bfd_boolean open_braket;
+ int size;
+ const struct arc_operand *operand;
+ int value;
+ struct arc_operand_iterator iter;
+ Elf_Internal_Ehdr *header = NULL;
+
+ if (info->disassembler_options)
+ {
+ parse_disassembler_options (info->disassembler_options);
+
+ /* Avoid repeated parsing of the options. */
+ info->disassembler_options = NULL;
+ }
+
+ memset (&iter, 0, sizeof (iter));
+ lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
+ highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
+
+ if (info->section && info->section->owner)
+ header = elf_elfheader (info->section->owner);
+
+ switch (info->mach)
+ {
+ case bfd_mach_arc_arc700:
+ isa_mask = ARC_OPCODE_ARC700;
break;
- case op_LD1:
- if (BIT (state->words[0],13))
- {
- instrName = "lr";
- decodingClass = CLASS_A4_LR;
- }
- else
- {
- switch (BITS (state->words[0], 10, 11))
- {
- case 0:
- instrName = "ld";
- state->_load_len = 4;
- break;
- case 1:
- instrName = "ldb";
- state->_load_len = 1;
- break;
- case 2:
- instrName = "ldw";
- state->_load_len = 2;
- break;
- default:
- instrName = "??? (1[3])";
- state->flow = invalid_instr;
- break;
- }
- decodingClass = CLASS_A4_LD1;
- }
+ case bfd_mach_arc_arc600:
+ isa_mask = ARC_OPCODE_ARC600;
break;
- case op_ST:
- if (BIT (state->words[0], 25))
- {
- instrName = "sr";
- decodingClass = CLASS_A4_SR;
- }
- else
+ case bfd_mach_arc_arcv2:
+ default:
+ isa_mask = ARC_OPCODE_ARCv2EM;
+ if ((header->e_flags & EF_ARC_MACH_MSK) == EF_ARC_CPU_ARCV2HS)
{
- switch (BITS (state->words[0], 22, 23))
- {
- case 0:
- instrName = "st";
- break;
- case 1:
- instrName = "stb";
- break;
- case 2:
- instrName = "stw";
- break;
- default:
- instrName = "??? (2[3])";
- state->flow = invalid_instr;
- break;
- }
- decodingClass = CLASS_A4_ST;
+ isa_mask = ARC_OPCODE_ARCv2HS;
+ /* FPU instructions are not extensions for HS. */
+ add_to_decodelist (FLOAT, SP);
+ add_to_decodelist (FLOAT, DP);
+ add_to_decodelist (FLOAT, CVT);
}
break;
+ }
+
+ /* This variable may be set by the instruction decoder. It suggests
+ the number of bytes objdump should display on a single line. If
+ the instruction decoder sets this, it should always set it to
+ the same value in order to get reasonable looking output. */
- case op_3:
- decodingClass = CLASS_A4_OP3_GENERAL; /* default for opcode 3... */
- switch (FIELDC (state->words[0]))
+ info->bytes_per_line = 8;
+
+ /* In the next lines, we set two info variables control the way
+ objdump displays the raw data. For example, if bytes_per_line is
+ 8 and bytes_per_chunk is 4, the output will look like this:
+ 00: 00000000 00000000
+ with the chunks displayed according to "display_endian". */
+
+ if (info->section
+ && !(info->section->flags & SEC_CODE))
+ {
+ /* This is not a CODE section. */
+ switch (info->section->size)
{
- case 0:
- instrName = "flag";
- decodingClass = CLASS_A4_FLAG;
- break;
- case 1:
- instrName = "asr";
- break;
- case 2:
- instrName = "lsr";
- break;
- case 3:
- instrName = "ror";
- break;
- case 4:
- instrName = "rrc";
- break;
- case 5:
- instrName = "sexb";
- break;
- case 6:
- instrName = "sexw";
- break;
- case 7:
- instrName = "extb";
- break;
- case 8:
- instrName = "extw";
- break;
- case 0x3f:
- {
- decodingClass = CLASS_A4_OP3_SUBOPC3F;
- switch (FIELDD (state->words[0]))
- {
- case 0:
- instrName = "brk";
- break;
- case 1:
- instrName = "sleep";
- break;
- case 2:
- instrName = "swi";
- break;
- default:
- instrName = "???";
- state->flow=invalid_instr;
- break;
- }
- }
+ case 1:
+ case 2:
+ case 4:
+ size = info->section->size;
break;
-
- /* ARC Extension Library Instructions
- NOTE: We assume that extension codes are these instrs. */
default:
- instrName = instruction_name (state,
- state->_opcode,
- FIELDC (state->words[0]),
- &flags);
- if (!instrName)
- {
- instrName = "???";
- state->flow = invalid_instr;
- }
- if (flags & IGNORE_FIRST_OPD)
- ignoreFirstOpd = 1;
+ size = (info->section->size & 0x01) ? 1 : 4;
break;
}
- break;
+ info->bytes_per_chunk = 1;
+ info->display_endian = info->endian;
+ }
+ else
+ {
+ size = 2;
+ info->bytes_per_chunk = 2;
+ info->display_endian = info->endian;
+ }
- case op_BC:
- instrName = "b";
- case op_BLC:
- if (!instrName)
- instrName = "bl";
- case op_LPC:
- if (!instrName)
- instrName = "lp";
- case op_JC:
- if (!instrName)
- {
- if (BITS (state->words[0],9,9))
- {
- instrName = "jl";
- is_linked = 1;
- }
- else
- {
- instrName = "j";
- is_linked = 0;
- }
- }
- condCodeIsPartOfName = 1;
- decodingClass = ((state->_opcode == op_JC) ? CLASS_A4_JC : CLASS_A4_BRANCH );
- state->isBranch = 1;
- break;
+ /* Read the insn into a host word. */
+ status = (*info->read_memory_func) (memaddr, buffer, size, info);
+ if (status != 0)
+ {
+ (*info->memory_error_func) (status, memaddr, info);
+ return -1;
+ }
- case op_ADD:
- case op_ADC:
- case op_AND:
- repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
+ if (info->section
+ && !(info->section->flags & SEC_CODE))
+ {
+ /* Data section. */
+ unsigned long data;
- switch (state->_opcode)
+ data = bfd_get_bits (buffer, size * 8,
+ info->display_endian == BFD_ENDIAN_BIG);
+ switch (size)
{
- case op_ADD:
- instrName = (repeatsOp ? "asl" : "add");
+ case 1:
+ (*info->fprintf_func) (info->stream, ".byte\t0x%02lx", data);
break;
- case op_ADC:
- instrName = (repeatsOp ? "rlc" : "adc");
+ case 2:
+ (*info->fprintf_func) (info->stream, ".short\t0x%04lx", data);
break;
- case op_AND:
- instrName = (repeatsOp ? "mov" : "and");
+ case 4:
+ (*info->fprintf_func) (info->stream, ".word\t0x%08lx", data);
break;
+ default:
+ abort ();
}
- break;
+ return size;
+ }
- case op_SUB: instrName = "sub";
- break;
- case op_SBC: instrName = "sbc";
- break;
- case op_OR: instrName = "or";
- break;
- case op_BIC: instrName = "bic";
- break;
+ insn_len = arc_insn_length (buffer[lowbyte], buffer[highbyte], info);
+ pr_debug ("instruction length = %d bytes\n", insn_len);
- case op_XOR:
- if (state->words[0] == 0x7fffffff)
- {
- /* NOP encoded as xor -1, -1, -1. */
- instrName = "nop";
- decodingClass = CLASS_A4_OP3_SUBOPC3F;
- }
- else
- instrName = "xor";
+ switch (insn_len)
+ {
+ case 2:
+ insn[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
break;
default:
- instrName = instruction_name (state,state->_opcode,0,&flags);
- /* if (instrName) printf("FLAGS=0x%x\n", flags); */
- if (!instrName)
+ /* An unknown instruction is treated as being length 4. This is
+ possibly not the best solution, but matches the behaviour that was
+ in place before the table based instruction length look-up was
+ introduced. */
+ case 4:
+ /* This is a long instruction: Read the remaning 2 bytes. */
+ status = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
+ if (status != 0)
{
- instrName = "???";
- state->flow=invalid_instr;
+ (*info->memory_error_func) (status, memaddr + 2, info);
+ return -1;
}
- if (flags & IGNORE_FIRST_OPD)
- ignoreFirstOpd = 1;
+ insn[0] = ARRANGE_ENDIAN (info, buffer);
break;
}
- fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
- flag = cond = is_shimm = is_limm = 0;
- state->nullifyMode = BR_exec_when_no_jump; /* 0 */
- signExtend = addrWriteBack = directMem = 0;
- usesAuxReg = 0;
+ /* Set some defaults for the insn info. */
+ info->insn_info_valid = 1;
+ info->branch_delay_insns = 0;
+ info->data_size = 0;
+ info->insn_type = dis_nonbranch;
+ info->target = 0;
+ info->target2 = 0;
+
+ /* FIXME to be moved in dissasemble_init_for_target. */
+ info->disassembler_needs_relocs = TRUE;
+
+ /* Find the first match in the opcode table. */
+ if (!find_format (memaddr, insn, &insn_len, isa_mask, info, &opcode, &iter))
+ return -1;
- switch (decodingClass)
+ if (!opcode)
{
- case CLASS_A4_ARITH:
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- if (!repeatsOp)
- CHECK_FIELD_C ();
- CHECK_FLAG_COND_NULLIFY ();
-
- write_instr_name ();
- if (!ignoreFirstOpd)
- {
- WRITE_FORMAT_x (A);
- WRITE_FORMAT_COMMA_x (B);
- if (!repeatsOp)
- WRITE_FORMAT_COMMA_x (C);
- WRITE_NOP_COMMENT ();
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- }
+ if (insn_len == 2)
+ (*info->fprintf_func) (info->stream, ".long %#04x", insn[0]);
else
- {
- WRITE_FORMAT_x (B);
- if (!repeatsOp)
- WRITE_FORMAT_COMMA_x (C);
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldB, fieldC);
- }
- write_comments ();
- break;
+ (*info->fprintf_func) (info->stream, ".long %#08x", insn[0]);
+
+ info->insn_type = dis_noninsn;
+ return insn_len;
+ }
- case CLASS_A4_OP3_GENERAL:
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
+ /* Print the mnemonic. */
+ (*info->fprintf_func) (info->stream, "%s", opcode->name);
- write_instr_name ();
- if (!ignoreFirstOpd)
+ /* Preselect the insn class. */
+ switch (opcode->insn_class)
+ {
+ case BRANCH:
+ case JUMP:
+ if (!strncmp (opcode->name, "bl", 2)
+ || !strncmp (opcode->name, "jl", 2))
{
- WRITE_FORMAT_x (A);
- WRITE_FORMAT_COMMA_x (B);
- WRITE_NOP_COMMENT ();
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB);
+ if (opcode->subclass == COND)
+ info->insn_type = dis_condjsr;
+ else
+ info->insn_type = dis_jsr;
}
else
{
- WRITE_FORMAT_x (B);
- arc_sprintf (state, state->operandBuffer, formatString, fieldB);
+ if (opcode->subclass == COND)
+ info->insn_type = dis_condbranch;
+ else
+ info->insn_type = dis_branch;
}
- write_comments ();
break;
-
- case CLASS_A4_FLAG:
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
- flag = 0; /* This is the FLAG instruction -- it's redundant. */
-
- write_instr_name ();
- WRITE_FORMAT_x (B);
- arc_sprintf (state, state->operandBuffer, formatString, fieldB);
- write_comments ();
+ case MEMORY:
+ info->insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */
break;
+ default:
+ info->insn_type = dis_nonbranch;
+ break;
+ }
- case CLASS_A4_BRANCH:
- fieldA = BITS (state->words[0],7,26) << 2;
- fieldA = (fieldA << 10) >> 10; /* Make it signed. */
- fieldA += addr + 4;
- CHECK_FLAG_COND_NULLIFY ();
- flag = 0;
-
- write_instr_name ();
- /* This address could be a label we know. Convert it. */
- if (state->_opcode != op_LPC /* LP */)
- {
- add_target (fieldA); /* For debugger. */
- state->flow = state->_opcode == op_BLC /* BL */
- ? direct_call
- : direct_jump;
- /* indirect calls are achieved by "lr blink,[status];
- lr dest<- func addr; j [dest]" */
- }
+ pr_debug ("%s: 0x%08x\n", opcode->name, opcode->opcode);
- strcat (formatString, "%s"); /* Address/label name. */
- arc_sprintf (state, state->operandBuffer, formatString,
- post_address (state, fieldA));
- write_comments ();
- break;
+ print_flags (opcode, insn, info);
- case CLASS_A4_JC:
- /* For op_JC -- jump to address specified.
- Also covers jump and link--bit 9 of the instr. word
- selects whether linked, thus "is_linked" is set above. */
- fieldA = 0;
- CHECK_FIELD_B ();
- CHECK_FLAG_COND_NULLIFY ();
+ if (opcode->operands[0] != 0)
+ (*info->fprintf_func) (info->stream, "\t");
- if (!fieldBisReg)
- {
- fieldAisReg = 0;
- fieldA = (fieldB >> 25) & 0x7F; /* Flags. */
- fieldB = (fieldB & 0xFFFFFF) << 2;
- state->flow = is_linked ? direct_call : direct_jump;
- add_target (fieldB);
- /* Screwy JLcc requires .jd mode to execute correctly
- but we pretend it is .nd (no delay slot). */
- if (is_linked && state->nullifyMode == BR_exec_when_jump)
- state->nullifyMode = BR_exec_when_no_jump;
- }
- else
- {
- state->flow = is_linked ? indirect_call : indirect_jump;
- /* We should also treat this as indirect call if NOT linked
- but the preceding instruction was a "lr blink,[status]"
- and we have a delay slot with "add blink,blink,2".
- For now we can't detect such. */
- state->register_for_indirect_jump = fieldB;
- }
+ need_comma = FALSE;
+ open_braket = FALSE;
- write_instr_name ();
- strcat (formatString,
- IS_REG (B) ? "[%r]" : "%s"); /* Address/label name. */
- if (fieldA != 0)
+ /* Now extract and print the operands. */
+ operand = NULL;
+ while (operand_iterator_next (&iter, &operand, &value))
+ {
+ if (open_braket && (operand->flags & ARC_OPERAND_BRAKET))
{
- fieldAisReg = 0;
- WRITE_FORMAT_COMMA_x (A);
+ (*info->fprintf_func) (info->stream, "]");
+ open_braket = FALSE;
+ continue;
}
- if (IS_REG (B))
- arc_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
- else
- arc_sprintf (state, state->operandBuffer, formatString,
- post_address (state, fieldB), fieldA);
- write_comments ();
- break;
- case CLASS_A4_LD0:
- /* LD instruction.
- B and C can be regs, or one (both?) can be limm. */
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
- CHECK_FIELD_C ();
- if (dbg)
- printf ("5:b reg %d %d c reg %d %d \n",
- fieldBisReg,fieldB,fieldCisReg,fieldC);
- state->_offset = 0;
- state->_ea_present = 1;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- else
- state->_offset += fieldB;
- if (fieldCisReg)
- state->ea_reg2 = fieldC;
- else
- state->_offset += fieldC;
- state->_mem_load = 1;
+ /* Only take input from real operands. */
+ if ((operand->flags & ARC_OPERAND_FAKE)
+ && !(operand->flags & ARC_OPERAND_BRAKET))
+ continue;
- directMem = BIT (state->words[0], 5);
- addrWriteBack = BIT (state->words[0], 3);
- signExtend = BIT (state->words[0], 0);
+ if ((operand->flags & ARC_OPERAND_IGNORE)
+ && (operand->flags & ARC_OPERAND_IR)
+ && value == -1)
+ continue;
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(A);
- if (fieldBisReg || fieldB != 0)
- WRITE_FORMAT_x_COMMA (B);
- else
- fieldB = fieldC;
-
- WRITE_FORMAT_x_RB (C);
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- write_comments ();
- break;
+ if (need_comma)
+ (*info->fprintf_func) (info->stream, ",");
- case CLASS_A4_LD1:
- /* LD instruction. */
- CHECK_FIELD_B ();
- CHECK_FIELD_A ();
- fieldC = FIELDD (state->words[0]);
-
- if (dbg)
- printf ("6:b reg %d %d c 0x%x \n",
- fieldBisReg, fieldB, fieldC);
- state->_ea_present = 1;
- state->_offset = fieldC;
- state->_mem_load = 1;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- /* Field B is either a shimm (same as fieldC) or limm (different!)
- Say ea is not present, so only one of us will do the name lookup. */
- else
- state->_offset += fieldB, state->_ea_present = 0;
-
- directMem = BIT (state->words[0],14);
- addrWriteBack = BIT (state->words[0],12);
- signExtend = BIT (state->words[0],9);
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB (A);
- if (!fieldBisReg)
+ if (!open_braket && (operand->flags & ARC_OPERAND_BRAKET))
{
- fieldB = state->_offset;
- WRITE_FORMAT_x_RB (B);
+ (*info->fprintf_func) (info->stream, "[");
+ open_braket = TRUE;
+ need_comma = FALSE;
+ continue;
}
- else
+
+ /* Print the operand as directed by the flags. */
+ if (operand->flags & ARC_OPERAND_IR)
{
- WRITE_FORMAT_x (B);
- if (fieldC != 0 && !BIT (state->words[0],13))
+ const char *rname;
+
+ assert (value >=0 && value < 64);
+ rname = arcExtMap_coreRegName (value);
+ if (!rname)
+ rname = regnames[value];
+ (*info->fprintf_func) (info->stream, "%s", rname);
+ if (operand->flags & ARC_OPERAND_TRUNCATE)
{
- fieldCisReg = 0;
- WRITE_FORMAT_COMMA_x_RB (C);
+ rname = arcExtMap_coreRegName (value + 1);
+ if (!rname)
+ rname = regnames[value + 1];
+ (*info->fprintf_func) (info->stream, "%s", rname);
}
+ }
+ else if (operand->flags & ARC_OPERAND_LIMM)
+ {
+ const char *rname = get_auxreg (opcode, value, isa_mask);
+ if (rname && open_braket)
+ (*info->fprintf_func) (info->stream, "%s", rname);
else
- WRITE_FORMAT_RB ();
+ {
+ (*info->fprintf_func) (info->stream, "%#x", value);
+ if (info->insn_type == dis_branch
+ || info->insn_type == dis_jsr)
+ info->target = (bfd_vma) value;
+ }
}
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldA, fieldB, fieldC);
- write_comments ();
- break;
-
- case CLASS_A4_ST:
- /* ST instruction. */
- CHECK_FIELD_B();
- CHECK_FIELD_C();
- fieldA = FIELDD(state->words[0]); /* shimm */
-
- /* [B,A offset] */
- if (dbg) printf("7:b reg %d %x off %x\n",
- fieldBisReg,fieldB,fieldA);
- state->_ea_present = 1;
- state->_offset = fieldA;
- if (fieldBisReg)
- state->ea_reg1 = fieldB;
- /* Field B is either a shimm (same as fieldA) or limm (different!)
- Say ea is not present, so only one of us will do the name lookup.
- (for is_limm we do the name translation here). */
- else
- state->_offset += fieldB, state->_ea_present = 0;
-
- directMem = BIT (state->words[0], 26);
- addrWriteBack = BIT (state->words[0], 24);
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(C);
+ else if (operand->flags & ARC_OPERAND_PCREL)
+ {
+ /* PCL relative. */
+ if (info->flags & INSN_HAS_RELOC)
+ memaddr = 0;
+ (*info->print_address_func) ((memaddr & ~3) + value, info);
- if (!fieldBisReg)
+ info->target = (bfd_vma) (memaddr & ~3) + value;
+ }
+ else if (operand->flags & ARC_OPERAND_SIGNED)
{
- fieldB = state->_offset;
- WRITE_FORMAT_x_RB (B);
+ const char *rname = get_auxreg (opcode, value, isa_mask);
+ if (rname && open_braket)
+ (*info->fprintf_func) (info->stream, "%s", rname);
+ else
+ (*info->fprintf_func) (info->stream, "%d", value);
}
else
{
- WRITE_FORMAT_x (B);
- if (fieldBisReg && fieldA != 0)
+ if (operand->flags & ARC_OPERAND_TRUNCATE
+ && !(operand->flags & ARC_OPERAND_ALIGNED32)
+ && !(operand->flags & ARC_OPERAND_ALIGNED16)
+ && value > 0 && value <= 14)
+ (*info->fprintf_func) (info->stream, "r13-%s",
+ regnames[13 + value - 1]);
+ else
{
- fieldAisReg = 0;
- WRITE_FORMAT_COMMA_x_RB(A);
+ const char *rname = get_auxreg (opcode, value, isa_mask);
+ if (rname && open_braket)
+ (*info->fprintf_func) (info->stream, "%s", rname);
+ else
+ (*info->fprintf_func) (info->stream, "%#x", value);
}
- else
- WRITE_FORMAT_RB();
}
- arc_sprintf (state, state->operandBuffer, formatString,
- fieldC, fieldB, fieldA);
- write_comments2 (fieldA);
- break;
-
- case CLASS_A4_SR:
- /* SR instruction */
- CHECK_FIELD_B();
- CHECK_FIELD_C();
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB(C);
- /* Try to print B as an aux reg if it is not a core reg. */
- usesAuxReg = 1;
- WRITE_FORMAT_x (B);
- WRITE_FORMAT_RB ();
- arc_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
- write_comments ();
- break;
-
- case CLASS_A4_OP3_SUBOPC3F:
- write_instr_name ();
- state->operandBuffer[0] = '\0';
- break;
- case CLASS_A4_LR:
- /* LR instruction */
- CHECK_FIELD_A ();
- CHECK_FIELD_B ();
-
- write_instr_name ();
- WRITE_FORMAT_x_COMMA_LB (A);
- /* Try to print B as an aux reg if it is not a core reg. */
- usesAuxReg = 1;
- WRITE_FORMAT_x (B);
- WRITE_FORMAT_RB ();
- arc_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
- write_comments ();
- break;
-
- default:
- mwerror (state, "Bad decoding class in ARC disassembler");
- break;
+ need_comma = TRUE;
}
- state->_cond = cond;
- return state->instructionLen = offset;
+ return insn_len;
}
-/* Returns the name the user specified core extension register. */
-
-static const char *
-_coreRegName(void * arg ATTRIBUTE_UNUSED, int regval)
+disassembler_ftype
+arc_get_disassembler (bfd *abfd)
{
- return arcExtMap_coreRegName (regval);
-}
-
-/* Returns the name the user specified AUX extension register. */
+ /* Read the extenssion insns and registers, if any. */
+ build_ARC_extmap (abfd);
+#ifdef DEBUG
+ dump_ARC_extmap ();
+#endif
-static const char *
-_auxRegName(void *_this ATTRIBUTE_UNUSED, int regval)
-{
- return arcExtMap_auxRegName(regval);
+ return print_insn_arc;
}
-/* Returns the name the user specified condition code name. */
+/* Disassemble ARC instructions. Used by debugger. */
-static const char *
-_condCodeName(void *_this ATTRIBUTE_UNUSED, int regval)
+struct arcDisState
+arcAnalyzeInstr (bfd_vma memaddr,
+ struct disassemble_info *info)
{
- return arcExtMap_condCodeName(regval);
-}
-
-/* Returns the name the user specified extension instruction. */
+ struct arcDisState ret;
+ memset (&ret, 0, sizeof (struct arcDisState));
+
+ ret.instructionLen = print_insn_arc (memaddr, info);
+
+#if 0
+ ret.words[0] = insn[0];
+ ret.words[1] = insn[1];
+ ret._this = &ret;
+ ret.coreRegName = _coreRegName;
+ ret.auxRegName = _auxRegName;
+ ret.condCodeName = _condCodeName;
+ ret.instName = _instName;
+#endif
-static const char *
-_instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags)
-{
- return arcExtMap_instName(majop, minop, flags);
+ return ret;
}
-/* Decode an instruction returning the size of the instruction
- in bytes or zero if unrecognized. */
-
-static int
-decodeInstr (bfd_vma address, /* Address of this instruction. */
- disassemble_info * info)
+void
+print_arc_disassembler_options (FILE *stream)
{
- int status;
- bfd_byte buffer[4];
- struct arcDisState s; /* ARC Disassembler state. */
- void *stream = info->stream; /* Output stream. */
- fprintf_ftype func = info->fprintf_func;
- int bytes;
-
- memset (&s, 0, sizeof(struct arcDisState));
-
- /* read first instruction */
- status = (*info->read_memory_func) (address, buffer, 4, info);
- if (status != 0)
- {
- (*info->memory_error_func) (status, address, info);
- return 0;
- }
- if (info->endian == BFD_ENDIAN_LITTLE)
- s.words[0] = bfd_getl32(buffer);
- else
- s.words[0] = bfd_getb32(buffer);
- /* Always read second word in case of limm. */
-
- /* We ignore the result since last insn may not have a limm. */
- status = (*info->read_memory_func) (address + 4, buffer, 4, info);
- if (info->endian == BFD_ENDIAN_LITTLE)
- s.words[1] = bfd_getl32(buffer);
- else
- s.words[1] = bfd_getb32(buffer);
-
- s._this = &s;
- s.coreRegName = _coreRegName;
- s.auxRegName = _auxRegName;
- s.condCodeName = _condCodeName;
- s.instName = _instName;
-
- /* Disassemble. */
- bytes = dsmOneArcInst (address, (void *)& s);
-
- /* Display the disassembly instruction. */
- (*func) (stream, "%08lx ", s.words[0]);
- (*func) (stream, " ");
- (*func) (stream, "%-10s ", s.instrBuffer);
-
- if (__TRANSLATION_REQUIRED (s))
- {
- bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
-
- (*info->print_address_func) ((bfd_vma) addr, info);
- (*func) (stream, "\n");
- }
- else
- (*func) (stream, "%s",s.operandBuffer);
-
- return s.instructionLen;
+ fprintf (stream, _("\n\
+The following ARC specific disassembler options are supported for use \n\
+with -M switch (multiple options should be separated by commas):\n"));
+
+ fprintf (stream, _("\
+ dsp Recognize DSP instructions.\n"));
+ fprintf (stream, _("\
+ spfp Recognize FPX SP instructions.\n"));
+ fprintf (stream, _("\
+ dpfp Recognize FPX DP instructions.\n"));
+ fprintf (stream, _("\
+ quarkse_em Recognize FPU QuarkSE-EM instructions.\n"));
+ fprintf (stream, _("\
+ fpuda Recognize double assist FPU instructions.\n"));
+ fprintf (stream, _("\
+ fpus Recognize single precision FPU instructions.\n"));
+ fprintf (stream, _("\
+ fpud Recognize double precision FPU instructions.\n"));
}
-/* Return the print_insn function to use.
- Side effect: load (possibly empty) extension section */
-disassembler_ftype
-arc_get_disassembler (void *ptr)
-{
- if (ptr)
- build_ARC_extmap (ptr);
- return decodeInstr;
-}
+/* Local variables:
+ eval: (c-set-style "gnu")
+ indent-tabs-mode: t
+ End: */
projects / deliverable / binutils-gdb.git / blobdiff