/* Opcode table for the ARC.
- Copyright 1994, 1995 Free Software Foundation, Inc.
- Contributed by Doug Evans (dje@cygnus.com).
-
- This program is free software; you can redistribute it and/or modify
+ Copyright (C) 1994-2016 Free Software Foundation, Inc.
+
+ Contributed by Claudiu Zissulescu (claziss@synopsys.com)
+
+ This file is part of libopcodes.
+
+ This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2, or (at your option)
+ the Free Software Foundation; either version 3, or (at your option)
any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
+ It is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ License for more details.
You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+ along with this program; if not, write to the Free Software Foundation,
+ Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-#include "ansidecl.h"
+#include "sysdep.h"
+#include <stdio.h>
+#include "bfd.h"
#include "opcode/arc.h"
-
-#define INSERT_FN(fn) \
-static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
- int, const struct arc_operand_value *, long, \
- const char **))
-#define EXTRACT_FN(fn) \
-static long fn PARAMS ((arc_insn *, const struct arc_operand *, \
- int, const struct arc_operand_value **, int *))
-
-INSERT_FN (insert_reg);
-INSERT_FN (insert_shimmfinish);
-INSERT_FN (insert_limmfinish);
-INSERT_FN (insert_shimmoffset);
-INSERT_FN (insert_shimmzero);
-INSERT_FN (insert_flag);
-INSERT_FN (insert_flagfinish);
-INSERT_FN (insert_cond);
-INSERT_FN (insert_forcelimm);
-INSERT_FN (insert_reladdr);
-INSERT_FN (insert_absaddr);
-INSERT_FN (insert_unopmacro);
-INSERT_FN (insert_multshift);
-
-EXTRACT_FN (extract_reg);
-EXTRACT_FN (extract_flag);
-EXTRACT_FN (extract_cond);
-EXTRACT_FN (extract_reladdr);
-EXTRACT_FN (extract_unopmacro);
-EXTRACT_FN (extract_multshift);
-
-/* Various types of ARC operands, including insn suffixes. */
-
-/* Insn format values:
-
- 'a' REGA register A field
- 'b' REGB register B field
- 'c' REGC register C field
- 'S' SHIMMFINISH finish inserting a shimm value
- 'L' LIMMFINISH finish inserting a limm value
- 'd' SHIMMOFFSET shimm offset in ld,st insns
- '0' SHIMMZERO 0 shimm value in ld,st insns
- 'f' FLAG F flag
- 'F' FLAGFINISH finish inserting the F flag
- 'G' FLAGINSN insert F flag in "flag" insn
- 'n' DELAY N field (nullify field)
- 'q' COND condition code field
- 'Q' FORCELIMM set `cond_p' to 1 to ensure a constant is a limm
- 'B' BRANCH branch address (22 bit pc relative)
- 'J' JUMP jump address (26 bit absolute)
- 'z' SIZE1 size field in ld a,[b,c]
- 'Z' SIZE10 size field in ld a,[b,shimm]
- 'y' SIZE22 size field in st c,[b,shimm]
- 'x' SIGN0 sign extend field ld a,[b,c]
- 'X' SIGN9 sign extend field ld a,[b,shimm]
- 'w' ADDRESS3 write-back field in ld a,[b,c]
- 'W' ADDRESS12 write-back field in ld a,[b,shimm]
- 'v' ADDRESS24 write-back field in st c,[b,shimm]
- 'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
- 'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
- 'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
- 'u' UNSIGNED unsigned multiply
- 's' SATURATION saturation limit in audio arc mac insn
- 'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
-
- The following modifiers may appear between the % and char (eg: %.f):
-
- '.' MODDOT '.' prefix must be present
- 'r' REG generic register value, for register table
- 'A' AUXREG auxiliary register in lr a,[b], sr c,[b]
-
- Fields are:
-
- CHAR BITS SHIFT FLAGS INSERT_FN EXTRACT_FN
-*/
-
-const struct arc_operand arc_operands[] =
+#include "opintl.h"
+#include "libiberty.h"
+
+/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
+ instructions. Support for this target is available when binutils is
+ configured and built for the 'arc*-mellanox-*-*' target. As far as
+ possible all ARC NPS400 features are built into all ARC target builds as
+ this reduces the chances that regressions might creep in. */
+
+/* Insert RB register into a 32-bit opcode. */
+static unsigned
+insert_rb (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
-/* place holder (??? not sure if needed) */
-#define UNUSED 0
- { 0 },
-
-/* register A or shimm/limm indicator */
-#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, 0, insert_reg, extract_reg },
-
-/* register B or shimm/limm indicator */
-#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, 0, insert_reg, extract_reg },
-
-/* register C or shimm/limm indicator */
-#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, 0, insert_reg, extract_reg },
-
-/* fake operand used to insert shimm value into most instructions */
-#define SHIMMFINISH (REGC + 1)
- { 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
-
-/* fake operand used to insert limm value into most instructions;
- this is also used for .word handling */
-#define LIMMFINISH (SHIMMFINISH + 1)
- { 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
-
-/* shimm operand when there is no reg indicator (ld,st) */
-#define SHIMMOFFSET (LIMMFINISH + 1)
- { 'd', 9, 0, ARC_OPERAND_SIGNED, insert_shimmoffset, 0 },
-
-/* 0 shimm operand for ld,st insns */
-#define SHIMMZERO (SHIMMOFFSET + 1)
- { '0', 9, 0, ARC_OPERAND_FAKE, insert_shimmzero, 0 },
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
-/* flag update bit (insertion is defered until we know how) */
-#define FLAG (SHIMMZERO + 1)
- { 'f', 1, 8, ARC_OPERAND_SUFFIX, insert_flag, extract_flag },
+static int
+extract_rb (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
-/* fake utility operand to finish 'f' suffix handling */
-#define FLAGFINISH (FLAG + 1)
- { 'F', 1, 8, ARC_OPERAND_FAKE, insert_flagfinish, 0 },
+ if (value == 0x3e && invalid)
+ *invalid = TRUE; /* A limm operand, it should be extracted in a
+ different way. */
-/* fake utility operand to set the 'f' flag for the "flag" insn */
-#define FLAGINSN (FLAGFINISH + 1)
- { 'G', 1, 8, ARC_OPERAND_FAKE, insert_flag, 0 },
+ return value;
+}
-/* branch delay types */
-#define DELAY (FLAGINSN + 1)
- { 'n', 2, 5, ARC_OPERAND_SUFFIX },
+static unsigned
+insert_rad (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value & 0x01)
+ *errmsg = _("Improper register value.");
-/* conditions */
-#define COND (DELAY + 1)
- { 'q', 5, 0, ARC_OPERAND_SUFFIX, insert_cond, extract_cond },
+ return insn | (value & 0x3F);
+}
-/* set `cond_p' to 1 to ensure a constant is treated as a limm */
-#define FORCELIMM (COND + 1)
- { 'Q', 0, 0, ARC_OPERAND_FAKE, insert_forcelimm },
+static unsigned
+insert_rcd (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value & 0x01)
+ *errmsg = _("Improper register value.");
-/* branch address; b, bl, and lp insns */
-#define BRANCH (FORCELIMM + 1)
- { 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
+ return insn | ((value & 0x3F) << 6);
+}
-/* jump address; j insn (this is basically the same as 'L' except that the
- value is right shifted by 2); this is also used for .word handling */
-#define JUMP (BRANCH + 1)
- { 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
+/* Dummy insert ZERO operand function. */
-/* size field, stored in bit 1,2 */
-#define SIZE1 (JUMP + 1)
- { 'z', 2, 1, ARC_OPERAND_SUFFIX },
+static unsigned
+insert_za (unsigned insn,
+ int value,
+ const char **errmsg)
+{
+ if (value)
+ *errmsg = _("operand is not zero");
+ return insn;
+}
-/* size field, stored in bit 10,11 */
-#define SIZE10 (SIZE1 + 1)
- { 'Z', 2, 10, ARC_OPERAND_SUFFIX, },
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
-/* size field, stored in bit 22,23 */
-#define SIZE22 (SIZE10 + 1)
- { 'y', 2, 22, ARC_OPERAND_SUFFIX, },
+static unsigned
+insert_Ybit (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value > 0)
+ insn |= 0x08;
-/* sign extend field, stored in bit 0 */
-#define SIGN0 (SIZE22 + 1)
- { 'x', 1, 0, ARC_OPERAND_SUFFIX },
+ return insn;
+}
-/* sign extend field, stored in bit 9 */
-#define SIGN9 (SIGN0 + 1)
- { 'X', 1, 9, ARC_OPERAND_SUFFIX },
+/* Insert Y-bit in bbit/br instructions. This function is called only
+ when solving fixups. */
-/* address write back, stored in bit 3 */
-#define ADDRESS3 (SIGN9 + 1)
- { 'w', 1, 3, ARC_OPERAND_SUFFIX },
+static unsigned
+insert_NYbit (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 0)
+ insn |= 0x08;
-/* address write back, stored in bit 12 */
-#define ADDRESS12 (ADDRESS3 + 1)
- { 'W', 1, 12, ARC_OPERAND_SUFFIX },
+ return insn;
+}
-/* address write back, stored in bit 24 */
-#define ADDRESS24 (ADDRESS12 + 1)
- { 'v', 1, 24, ARC_OPERAND_SUFFIX },
+/* Insert H register into a 16-bit opcode. */
-/* cache bypass, stored in bit 5 */
-#define CACHEBYPASS5 (ADDRESS24 + 1)
- { 'e', 1, 5, ARC_OPERAND_SUFFIX },
-
-/* cache bypass, stored in bit 14 */
-#define CACHEBYPASS14 (CACHEBYPASS5 + 1)
- { 'E', 1, 14, ARC_OPERAND_SUFFIX },
-
-/* cache bypass, stored in bit 26 */
-#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
- { 'D', 1, 26, ARC_OPERAND_SUFFIX },
-
-/* unsigned multiply */
-#define UNSIGNED (CACHEBYPASS26 + 1)
- { 'u', 1, 27, ARC_OPERAND_SUFFIX },
-
-/* unsigned multiply */
-#define SATURATION (UNSIGNED + 1)
- { 's', 1, 28, ARC_OPERAND_SUFFIX },
-
-/* unop macro, used to copy REGB to REGC */
-#define UNOPMACRO (SATURATION + 1)
- { 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
-
-/* '.' modifier ('.' required). */
-#define MODDOT (UNOPMACRO + 1)
- { '.', 1, 0, ARC_MOD_DOT },
-
-/* Dummy 'r' modifier for the register table.
- It's called a "dummy" because there's no point in inserting an 'r' into all
- the %a/%b/%c occurrences in the insn table. */
-#define REG (MODDOT + 1)
- { 'r', 6, 0, ARC_MOD_REG },
+static unsigned
+insert_rhv1 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
+}
-/* Known auxiliary register modifier (stored in shimm field). */
-#define AUXREG (REG + 1)
- { 'A', 9, 0, ARC_MOD_AUXREG },
+static int
+extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
-/* end of list place holder */
- { 0 }
-};
-\f
-/* Given a format letter, yields the index into `arc_operands'.
- eg: arc_operand_map['a'] = REGA. */
-unsigned char arc_operand_map[256];
-
-#define I(x) (((x) & 31) << 27)
-#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA)
-#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB)
-#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
-#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-
-/* ARC instructions (sorted by at least the first letter, and equivalent
- opcodes kept together).
-
- By recording the insns this way, the table is not hashable on the opcode.
- That's not a real loss though as there are only a few entries for each
- insn (ld/st being the exception), which are quickly found and since
- they're stored together (eg: all `ld' variants are together) very little
- time is spent on the opcode itself. The slow part is parsing the options,
- but that's always going to be slow.
-
- Longer versions of insns must appear before shorter ones (if gas sees
- "lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
- junk).
-
- This table is best viewed on a wide screen (161 columns).
- I'd prefer to keep it this way. */
-
-/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
- a more general facility for dealing with macros which could be used if
- we need to. */
-/* ??? As an experiment, the "mov" macro appears at the start so it is
- prefered to "and" when disassembling. At present, the table needn't be
- sorted, though all opcodes with the same first letter must be kept
- together. */
-
-const struct arc_opcode arc_opcodes[] = {
- { "mac%u%.s%.q%.f %a,%b,%c%F%S%L", I(-4), I(24), ARC_MACH_AUDIO },
- /* Note that "mov" is really an "and". */
- { "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
- { "mul%u%.q%.f %a,%b,%c%F%S%L", I(-2), I(28), ARC_MACH_AUDIO },
- /* ??? This insn allows an optional "0," preceding the args. */
- /* We can't use %u here because it's not a suffix (the "64" is in the way). */
- { "mul64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(20)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- { "mulu64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(21)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
-
- { "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
- { "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
- { "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
- { "asl%.q%.f %a,%b,%c%F%S%L", I(-1), I(16), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- /* Note that "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "asr%.q%.f %a,%b,%c%F%S%L", I(-1), I(18), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- { "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
- { "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
- { "b%q%.n %B", I(-1), I(4) },
- { "bl%q%.n %B", I(-1), I(5) },
- { "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
- { "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
- { "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
- /* %Q: force cond_p=1 --> no shimm values */
- /* ??? This insn allows an optional flags spec. */
- { "j%q%Q%.n%.f %b%J", I(-1)+A(-1)+C(-1)+R(-1,7,1), I(7)+A(0)+C(0)+R(0,7,1) },
- /* Put opcode 1 ld insns first so shimm gets prefered over limm. */
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
- { "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
- { "ld%z%.x%.w%.e %a,[%b,%c]", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
- { "lp%q%.n %B", I(-1), I(6), },
- { "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
- /* Note that "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "lsr%.q%.f %a,%b,%c%F%S%L", I(-1), I(17), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- { "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
- /* Note that "nop" is really an "xor". */
- { "nop", 0xffffffff, 0x7fffffff },
- { "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
- /* ??? The %a here should be %p or something. */
- { "padc%.q%.f %a,%b,%c%F%S%L", I(-1), I(25), ARC_MACH_GRAPHICS },
- { "padd%.q%.f %a,%b,%c%F%S%L", I(-1), I(24), ARC_MACH_GRAPHICS },
- /* Note that "pmov" is really a "pand". */
- { "pmov%.q%.f %a,%b%F%S%L%U", I(-1), I(28), ARC_MACH_GRAPHICS },
- { "pand%.q%.f %a,%b,%c%F%S%L", I(-1), I(28), ARC_MACH_GRAPHICS },
- { "psbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(27), ARC_MACH_GRAPHICS },
- { "psub%.q%.f %a,%b,%c%F%S%L", I(-1), I(26), ARC_MACH_GRAPHICS },
- /* Note that "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
- { "ror%.q%.f %a,%b,%c%F%S%L", I(-1), I(19), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- { "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
- { "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
- { "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
- { "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
- { "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
- { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
- /* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "st%y%.v%.D %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) },
- { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) },
- { "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
- { "swap%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(9), ARC_MACH_AUDIO },
- { "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
-};
-const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
-
-const struct arc_operand_value arc_reg_names[] =
-{
- /* Sort this so that the first 61 entries are sequential.
- IE: For each i (i<61), arc_reg_names[i].value == i. */
-
- { "r0", 0, REG }, { "r1", 1, REG }, { "r2", 2, REG }, { "r3", 3, REG },
- { "r4", 4, REG }, { "r5", 5, REG }, { "r6", 6, REG }, { "r7", 7, REG },
- { "r8", 8, REG }, { "r9", 9, REG }, { "r10", 10, REG }, { "r11", 11, REG },
- { "r12", 12, REG }, { "r13", 13, REG }, { "r14", 14, REG }, { "r15", 15, REG },
- { "r16", 16, REG }, { "r17", 17, REG }, { "r18", 18, REG }, { "r19", 19, REG },
- { "r20", 20, REG }, { "r21", 21, REG }, { "r22", 22, REG }, { "r23", 23, REG },
- { "r24", 24, REG }, { "r25", 25, REG }, { "r26", 26, REG }, { "fp", 27, REG },
- { "sp", 28, REG }, { "ilink1", 29, REG }, { "ilink2", 30, REG }, { "blink", 31, REG },
- { "r32", 32, REG }, { "r33", 33, REG }, { "r34", 34, REG }, { "r35", 35, REG },
- { "r36", 36, REG }, { "r37", 37, REG }, { "r38", 38, REG }, { "r39", 39, REG },
- { "r40", 40, REG }, { "r41", 41, REG }, { "r42", 42, REG }, { "r43", 43, REG },
- { "r44", 44, REG }, { "r45", 45, REG }, { "r46", 46, REG }, { "r47", 47, REG },
- { "r48", 48, REG }, { "r49", 49, REG }, { "r50", 50, REG }, { "r51", 51, REG },
- { "r52", 52, REG }, { "r53", 53, REG }, { "r54", 54, REG }, { "r55", 55, REG },
- { "r56", 56, REG }, { "r57", 57, REG }, { "r58", 58, REG }, { "r59", 59, REG },
- { "lp_count", 60, REG },
-
- /* I'd prefer to output these as "fp" and "sp" by default, but we still need
- to recognize the canonical values. */
- { "r27", 27, REG }, { "r28", 28, REG },
-
- /* Standard auxiliary registers. */
- { "status", 0, AUXREG },
- { "semaphore", 1, AUXREG },
- { "lp_start", 2, AUXREG },
- { "lp_end", 3, AUXREG },
- { "identity", 4, AUXREG },
- { "debug", 5, AUXREG },
-
- /* Host ARC Extensions. */
- { "mlo", 57, REG, ARC_MACH_HOST },
- { "mmid", 58, REG, ARC_MACH_HOST },
- { "mhi", 59, REG, ARC_MACH_HOST },
- { "ivic", 0x10, AUXREG, ARC_MACH_HOST },
- { "ivdc", 0x11, AUXREG, ARC_MACH_HOST },
- { "ivdcn", 0x12, AUXREG, ARC_MACH_HOST },
- { "flushd", 0x13, AUXREG, ARC_MACH_HOST },
- { "saha", 0x14, AUXREG, ARC_MACH_HOST },
- { "gahd", 0x15, AUXREG, ARC_MACH_HOST },
- { "aahd", 0x16, AUXREG, ARC_MACH_HOST },
- { "rrcr", 0x17, AUXREG, ARC_MACH_HOST },
- { "rpcr", 0x18, AUXREG, ARC_MACH_HOST },
- { "flushdn", 0x19, AUXREG, ARC_MACH_HOST },
- { "dbgad1", 0x1a, AUXREG, ARC_MACH_HOST },
- { "dbgad2", 0x1b, AUXREG, ARC_MACH_HOST },
- { "dbgmde", 0x1c, AUXREG, ARC_MACH_HOST },
- { "dbgstat", 0x1d, AUXREG, ARC_MACH_HOST },
- { "wag", 0x1e, AUXREG, ARC_MACH_HOST },
- { "mulhi", 0x1f, AUXREG, ARC_MACH_HOST },
- { "intwide", 0x20, AUXREG, ARC_MACH_HOST },
- { "intgen", 0x21, AUXREG, ARC_MACH_HOST },
- { "rfsh_n", 0x22, AUXREG, ARC_MACH_HOST },
-
- /* Graphics ARC Extensions. */
- { "mlo", 57, REG, ARC_MACH_GRAPHICS },
- { "mmid", 58, REG, ARC_MACH_GRAPHICS },
- { "mhi", 59, REG, ARC_MACH_GRAPHICS },
- { "ivic", 0x10, AUXREG, ARC_MACH_GRAPHICS },
- { "wag", 0x1e, AUXREG, ARC_MACH_GRAPHICS },
- { "mulhi", 0x1f, AUXREG, ARC_MACH_GRAPHICS },
- { "intwide", 0x20, AUXREG, ARC_MACH_GRAPHICS },
- { "intgen", 0x21, AUXREG, ARC_MACH_GRAPHICS },
- { "pix", 0x100, AUXREG, ARC_MACH_GRAPHICS },
- { "scratch", 0x120, AUXREG, ARC_MACH_GRAPHICS },
-
- /* Audio ARC Extensions. */
- { "macmode", 39, REG, ARC_MACH_AUDIO },
- { "rs1", 40, REG, ARC_MACH_AUDIO },
- { "rs1n", 41, REG, ARC_MACH_AUDIO },
- { "rs1start", 42, REG, ARC_MACH_AUDIO },
- { "rs1size", 43, REG, ARC_MACH_AUDIO },
- { "rs1delta", 44, REG, ARC_MACH_AUDIO },
- { "rs1pos", 45, REG, ARC_MACH_AUDIO },
- { "rd1", 46, REG, ARC_MACH_AUDIO },
- { "rd1n", 47, REG, ARC_MACH_AUDIO },
- { "rd1d", 48, REG, ARC_MACH_AUDIO },
- { "rd1pos", 49, REG, ARC_MACH_AUDIO },
- { "rs2", 50, REG, ARC_MACH_AUDIO },
- { "rs2n", 51, REG, ARC_MACH_AUDIO },
- { "rs2start", 52, REG, ARC_MACH_AUDIO },
- { "rs2size", 53, REG, ARC_MACH_AUDIO },
- { "rs2delta", 54, REG, ARC_MACH_AUDIO },
- { "rs2pos", 55, REG, ARC_MACH_AUDIO },
- { "rd2", 56, REG, ARC_MACH_AUDIO },
- { "rd2n", 57, REG, ARC_MACH_AUDIO },
- { "rd2d", 58, REG, ARC_MACH_AUDIO },
- { "rd2pos", 59, REG, ARC_MACH_AUDIO },
- { "ivic", 0x10, AUXREG, ARC_MACH_AUDIO },
- { "wag", 0x1e, AUXREG, ARC_MACH_AUDIO },
- { "intwide", 0x20, AUXREG, ARC_MACH_AUDIO },
- { "intgen", 0x21, AUXREG, ARC_MACH_AUDIO },
- { "bm_sstart", 0x30, AUXREG, ARC_MACH_AUDIO },
- { "bm_length", 0x31, AUXREG, ARC_MACH_AUDIO },
- { "bm_rstart", 0x32, AUXREG, ARC_MACH_AUDIO },
- { "bm_go", 0x33, AUXREG, ARC_MACH_AUDIO },
- { "xtp_newval", 0x40, AUXREG, ARC_MACH_AUDIO },
- { "sram", 0x400, AUXREG, ARC_MACH_AUDIO },
- { "reg_file", 0x800, AUXREG, ARC_MACH_AUDIO },
-};
-const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
-
-/* The suffix table.
- Operands with the same name must be stored together. */
-
-const struct arc_operand_value arc_suffixes[] =
-{
- /* Entry 0 is special, default values aren't printed by the disassembler. */
- { "", 0, -1 },
- { "al", 0, COND },
- { "ra", 0, COND },
- { "eq", 1, COND },
- { "z", 1, COND },
- { "ne", 2, COND },
- { "nz", 2, COND },
- { "p", 3, COND },
- { "pl", 3, COND },
- { "n", 4, COND },
- { "mi", 4, COND },
- { "c", 5, COND },
- { "cs", 5, COND },
- { "lo", 5, COND },
- { "nc", 6, COND },
- { "cc", 6, COND },
- { "hs", 6, COND },
- { "v", 7, COND },
- { "vs", 7, COND },
- { "nv", 8, COND },
- { "vc", 8, COND },
- { "gt", 9, COND },
- { "ge", 10, COND },
- { "lt", 11, COND },
- { "le", 12, COND },
- { "hi", 13, COND },
- { "ls", 14, COND },
- { "pnz", 15, COND },
- { "f", 1, FLAG },
- { "nd", 0, DELAY },
- { "d", 1, DELAY },
- { "jd", 2, DELAY },
-/*{ "b", 7, SIZEEXT },*/
-/*{ "b", 5, SIZESEX },*/
- { "b", 1, SIZE1 },
- { "b", 1, SIZE10 },
- { "b", 1, SIZE22 },
-/*{ "w", 8, SIZEEXT },*/
-/*{ "w", 6, SIZESEX },*/
- { "w", 2, SIZE1 },
- { "w", 2, SIZE10 },
- { "w", 2, SIZE22 },
- { "x", 1, SIGN0 },
- { "x", 1, SIGN9 },
- { "a", 1, ADDRESS3 },
- { "a", 1, ADDRESS12 },
- { "a", 1, ADDRESS24 },
- { "di", 1, CACHEBYPASS5 },
- { "di", 1, CACHEBYPASS14 },
- { "di", 1, CACHEBYPASS26 },
-
- /* Audio ARC Extensions. */
- /* ??? The values here are guesses. */
- { "ss", 16, COND, ARC_MACH_AUDIO },
- { "sc", 17, COND, ARC_MACH_AUDIO },
- { "mh", 18, COND, ARC_MACH_AUDIO },
- { "ml", 19, COND, ARC_MACH_AUDIO },
-};
-const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
-\f
-/* Configuration flags. */
+ return value;
+}
-/* Various ARC_HAVE_XXX bits. */
-static int cpu_type;
+/* Insert H register into a 16-bit opcode. */
-/* Translate a bfd_mach_arc_xxx value to a ARC_MACH_XXX value. */
+static unsigned
+insert_rhv2 (unsigned insn,
+ int value,
+ const char **errmsg)
+{
+ if (value == 0x1E)
+ *errmsg =
+ _("Register R30 is a limm indicator for this type of instruction.");
+ return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
+}
-int
-arc_get_opcode_mach (bfd_mach, big_p)
- int bfd_mach, big_p;
+static int
+extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- static int mach_type_map[] =
- {
- ARC_MACH_BASE, ARC_MACH_HOST, ARC_MACH_GRAPHICS, ARC_MACH_AUDIO
- };
+ int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
- return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
+ return value;
}
-/* Initialize any tables that need it.
- Must be called once at start up (or when first needed).
-
- FLAGS is a set of bits that say what version of the cpu we have,
- and in particular at least (one of) ARC_MACH_XXX. */
+static unsigned
+insert_r0 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 0)
+ *errmsg = _("Register must be R0.");
+ return insn;
+}
-void
-arc_opcode_init_tables (flags)
- int flags;
+static int
+extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- register int i,n;
- static int map_init_p = 0;
+ return 0;
+}
- cpu_type = flags;
- /* We may be intentionally called more than once (for example gdb will call
- us each time the user switches cpu). This table only needs to be init'd
- once though. */
- if (!map_init_p)
- {
- memset (arc_operand_map, 0, sizeof (arc_operand_map));
- n = sizeof (arc_operands) / sizeof (arc_operands[0]);
- for (i = 0; i < n; i++)
- arc_operand_map[arc_operands[i].fmt] = i;
- map_init_p = 1;
- }
+static unsigned
+insert_r1 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 1)
+ *errmsg = _("Register must be R1.");
+ return insn;
}
-/* Return non-zero if OPCODE is supported on the specified cpu.
- Cpu selection is made when calling `arc_opcode_init_tables'. */
+static int
+extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 1;
+}
-int
-arc_opcode_supported (opcode)
- const struct arc_opcode *opcode;
+static unsigned
+insert_r2 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- if (ARC_OPCODE_CPU (opcode->flags) == 0)
- return 1;
- if (ARC_OPCODE_CPU (opcode->flags) & ARC_HAVE_CPU (cpu_type))
- return 1;
- return 0;
+ if (value != 2)
+ *errmsg = _("Register must be R2.");
+ return insn;
}
-/* Return non-zero if OPVAL is supported on the specified cpu.
- Cpu selection is made when calling `arc_opcode_init_tables'. */
+static int
+extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 2;
+}
-int
-arc_opval_supported (opval)
- const struct arc_operand_value *opval;
+static unsigned
+insert_r3 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- if (ARC_OPVAL_CPU (opval->flags) == 0)
- return 1;
- if (ARC_OPVAL_CPU (opval->flags) & ARC_HAVE_CPU (cpu_type))
- return 1;
- return 0;
+ if (value != 3)
+ *errmsg = _("Register must be R3.");
+ return insn;
}
-\f
-/* Nonzero if we've seen an 'f' suffix (in certain insns). */
-static int flag_p;
-/* Nonzero if we've finished processing the 'f' suffix. */
-static int flagshimm_handled_p;
+static int
+extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 3;
+}
-/* Nonzero if we've seen a 'q' suffix (condition code). */
-static int cond_p;
+static unsigned
+insert_sp (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 28)
+ *errmsg = _("Register must be SP.");
+ return insn;
+}
-/* Nonzero if we've inserted a shimm. */
-static int shimm_p;
+static int
+extract_sp (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 28;
+}
-/* The value of the shimm we inserted (each insn only gets one but it can
- appear multiple times. */
-static int shimm;
+static unsigned
+insert_gp (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 26)
+ *errmsg = _("Register must be GP.");
+ return insn;
+}
-/* Nonzero if we've inserted a limm (during assembly) or seen a limm
- (during disassembly). */
-static int limm_p;
+static int
+extract_gp (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 26;
+}
-/* The value of the limm we inserted. Each insn only gets one but it can
- appear multiple times. */
-static long limm;
-\f
-/* Insertion functions. */
+static unsigned
+insert_pcl (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 63)
+ *errmsg = _("Register must be PCL.");
+ return insn;
+}
-/* Called by the assembler before parsing an instruction. */
+static int
+extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 63;
+}
-void
-arc_opcode_init_insert ()
+static unsigned
+insert_blink (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- flag_p = 0;
- flagshimm_handled_p = 0;
- cond_p = 0;
- shimm_p = 0;
- limm_p = 0;
+ if (value != 31)
+ *errmsg = _("Register must be BLINK.");
+ return insn;
}
-/* Called by the assembler to see if the insn has a limm operand.
- Also called by the disassembler to see if the insn contains a limm. */
+static int
+extract_blink (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 31;
+}
-int
-arc_opcode_limm_p (limmp)
- long *limmp;
+static unsigned
+insert_ilink1 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- if (limmp)
- *limmp = limm;
- return limm_p;
+ if (value != 29)
+ *errmsg = _("Register must be ILINK1.");
+ return insn;
}
-/* Insert a value into a register field.
- If REG is NULL, then this is actually a constant.
+static int
+extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return 29;
+}
- We must also handle auxiliary registers for lr/sr insns. */
+static unsigned
+insert_ilink2 (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 30)
+ *errmsg = _("Register must be ILINK2.");
+ return insn;
+}
-static arc_insn
-insert_reg (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static int
+extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- static char buf[100];
+ return 30;
+}
- if (!reg)
- {
- /* We have a constant that also requires a value stored in a register
- field. Handle these by updating the register field and saving the
- value for later handling by either %S (shimm) or %L (limm). */
-
- /* Try to use a shimm value before a limm one. */
- if (ARC_SHIMM_CONST_P (value)
- /* If we've seen a conditional suffix we have to use a limm. */
- && !cond_p
- /* If we already have a shimm value that is different than ours
- we have to use a limm. */
- && (!shimm_p || shimm == value))
- {
- int marker = flag_p ? ARC_REG_SHIMM_UPDATE : ARC_REG_SHIMM;
- flagshimm_handled_p = 1;
- shimm_p = 1;
- shimm = value;
- insn |= marker << operand->shift;
- /* insn |= value & 511; - done later */
- }
- /* We have to use a limm. If we've already seen one they must match. */
- else if (!limm_p || limm == value)
- {
- limm_p = 1;
- limm = value;
- insn |= ARC_REG_LIMM << operand->shift;
- /* The constant is stored later. */
- }
- else
- {
- *errmsg = "unable to fit different valued constants into instruction";
- }
- }
- else
+static unsigned
+insert_ras (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
{
- /* We have to handle both normal and auxiliary registers. */
-
- if (reg->type == AUXREG)
- {
- if (!(mods & ARC_MOD_AUXREG))
- *errmsg = "auxiliary register not allowed here";
- else
- {
- insn |= ARC_REG_SHIMM << operand->shift;
- insn |= reg->value << arc_operands[reg->type].shift;
- }
- }
- else
- {
- /* We should never get an invalid register number here. */
- if ((unsigned int) reg->value > 60)
- {
- sprintf (buf, "invalid register number `%d'", reg->value);
- *errmsg = buf;
- }
- else
- insn |= reg->value << operand->shift;
- }
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8);
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
}
-
return insn;
}
-/* Called when we see an 'f' flag. */
-
-static arc_insn
-insert_flag (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static int
+extract_ras (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- /* We can't store anything in the insn until we've parsed the registers.
- Just record the fact that we've got this flag. `insert_reg' will use it
- to store the correct value (ARC_REG_SHIMM_UPDATE or bit 0x100). */
- flag_p = 1;
+ int value = insn & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
+static unsigned
+insert_rbs (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 8;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 8;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
+ }
return insn;
}
-/* Called after completely building an insn to ensure the 'f' flag gets set
- properly. This is needed because we don't know how to set this flag until
- we've parsed the registers. */
+static int
+extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
-static arc_insn
-insert_flagfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static unsigned
+insert_rcs (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- if (flag_p && !flagshimm_handled_p)
+ switch (value)
{
- if (shimm_p)
- abort ();
- flagshimm_handled_p = 1;
- insn |= (1 << operand->shift);
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 5;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= ((value - 8)) << 5;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
}
return insn;
}
-/* Called when we see a conditional flag (eg: .eq). */
-
-static arc_insn
-insert_cond (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static int
+extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- cond_p = 1;
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
+ int value = (insn >> 5) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
}
-/* Used in the "j" instruction to prevent constants from being interpreted as
- shimm values (which the jump insn doesn't accept). This can also be used
- to force the use of limm values in other situations (eg: ld r0,[foo] uses
- this).
- ??? The mechanism is sound. Access to it is a bit klunky right now. */
-
-static arc_insn
-insert_forcelimm (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
-{
- cond_p = 1;
+static unsigned
+insert_simm3s (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ int tmp = 0;
+ switch (value)
+ {
+ case -1:
+ tmp = 0x07;
+ break;
+ case 0:
+ tmp = 0x00;
+ break;
+ case 1:
+ tmp = 0x01;
+ break;
+ case 2:
+ tmp = 0x02;
+ break;
+ case 3:
+ tmp = 0x03;
+ break;
+ case 4:
+ tmp = 0x04;
+ break;
+ case 5:
+ tmp = 0x05;
+ break;
+ case 6:
+ tmp = 0x06;
+ break;
+ default:
+ *errmsg = _("Accepted values are from -1 to 6.");
+ break;
+ }
+
+ insn |= tmp << 8;
return insn;
}
-/* Used in ld/st insns to handle the shimm offset field. */
+static int
+extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 8) & 0x07;
+ if (value == 7)
+ return -1;
+ else
+ return value;
+}
-static arc_insn
-insert_shimmoffset (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static unsigned
+insert_rrange (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ int reg1 = (value >> 16) & 0xFFFF;
+ int reg2 = value & 0xFFFF;
+ if (reg1 != 13)
+ {
+ *errmsg = _("First register of the range should be r13.");
+ return insn;
+ }
+ if (reg2 < 13 || reg2 > 26)
+ {
+ *errmsg = _("Last register of the range doesn't fit.");
+ return insn;
+ }
+ insn |= ((reg2 - 12) & 0x0F) << 1;
return insn;
}
-/* Used in ld/st insns when the shimm offset is 0. */
+static int
+extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return (insn >> 1) & 0x0F;
+}
-static arc_insn
-insert_shimmzero (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static unsigned
+insert_fpel (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- shimm_p = 1;
- shimm = 0;
+ if (value != 27)
+ {
+ *errmsg = _("Invalid register number, should be fp.");
+ return insn;
+ }
+
+ insn |= 0x0100;
return insn;
}
-/* Called at the end of processing normal insns (eg: add) to insert a shimm
- value (if present) into the insn. */
-
-static arc_insn
-insert_shimmfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static int
+extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- if (shimm_p)
- insn |= (shimm & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
+ return (insn & 0x0100) ? 27 : -1;
}
-/* Called at the end of processing normal insns (eg: add) to insert a limm
- value (if present) into the insn.
-
- Note that this function is only intended to handle instructions (with 4 byte
- immediate operands). It is not intended to handle data. */
-
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
- caller must do that. The extract fns take a pointer to two words. The
- insert fns could be converted and then we could do something useful, but
- then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them. */
-
-static arc_insn
-insert_limmfinish (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
-{
- if (limm_p)
- /* FIXME: put an abort here and see what happens. */
- ; /* nothing to do, gas does it */
+static unsigned
+insert_blinkel (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value != 31)
+ {
+ *errmsg = _("Invalid register number, should be blink.");
+ return insn;
+ }
+
+ insn |= 0x0200;
return insn;
}
-/* Called at the end of unary operand macros to copy the B field to C. */
+static int
+extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return (insn & 0x0200) ? 31 : -1;
+}
-static arc_insn
-insert_unopmacro (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static unsigned
+insert_pclel (unsigned insn,
+ int value,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- insn |= ((insn >> ARC_SHIFT_REGB) & ARC_MASK_REG) << operand->shift;
+ if (value != 63)
+ {
+ *errmsg = _("Invalid register number, should be pcl.");
+ return insn;
+ }
+
+ insn |= 0x0400;
return insn;
}
-/* Insert a relative address for a branch insn (b, bl, or lp). */
-
-static arc_insn
-insert_reladdr (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
+static int
+extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- if (value & 3)
- *errmsg = "branch address not on 4 byte boundary";
- insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
- return insn;
+ return (insn & 0x0400) ? 63 : -1;
}
-/* Insert a limm value as a 26 bit address right shifted 2 into the insn.
-
- Note that this function is only intended to handle instructions (with 4 byte
- immediate operands). It is not intended to handle data. */
-
-/* ??? Actually, there's nothing for us to do as we can't call frag_more, the
- caller must do that. The extract fns take a pointer to two words. The
- insert fns could be converted and then we could do something useful, but
- then the reloc handlers would have to know to work on the second word of
- a 2 word quantity. That's too much so we don't handle them. */
-
-static arc_insn
-insert_absaddr (insn, operand, mods, reg, value, errmsg)
- arc_insn insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value *reg;
- long value;
- const char **errmsg;
-{
- if (limm_p)
- /* FIXME: put an abort here and see what happens. */
- ; /* nothing to do */
+#define INSERT_W6
+/* mask = 00000000000000000000111111000000
+ insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
+static unsigned
+insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 0) & 0x003f) << 6;
+
return insn;
}
-\f
-/* Extraction functions.
- The suffix extraction functions' return value is redundant since it can be
- obtained from (*OPVAL)->value. However, the boolean suffixes don't have
- a suffix table entry for the "false" case, so values of zero must be
- obtained from the return value (*OPVAL == NULL). */
+#define EXTRACT_W6
+/* mask = 00000000000000000000111111000000. */
+static int
+extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ unsigned value = 0;
-static const struct arc_operand_value *lookup_register (int type, long regno);
+ value |= ((insn >> 6) & 0x003f) << 0;
-/* Called by the disassembler before printing an instruction. */
+ return value;
+}
-void
-arc_opcode_init_extract ()
+#define INSERT_G_S
+/* mask = 0000011100022000
+ insn = 01000ggghhhGG0HH. */
+static unsigned
+insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
{
- flag_p = 0;
- flagshimm_handled_p = 0;
- shimm_p = 0;
- limm_p = 0;
+ insn |= ((value >> 0) & 0x0007) << 8;
+ insn |= ((value >> 3) & 0x0003) << 3;
+
+ return insn;
}
-/* As we're extracting registers, keep an eye out for the 'f' indicator
- (ARC_REG_SHIMM_UPDATE). If we find a register (not a constant marker,
- like ARC_REG_SHIMM), set OPVAL so our caller will know this is a register.
+#define EXTRACT_G_S
+/* mask = 0000011100022000. */
+static int
+extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
- We must also handle auxiliary registers for lr/sr insns. They are just
- constants with special names. */
+ value |= ((insn >> 8) & 0x0007) << 0;
+ value |= ((insn >> 3) & 0x0003) << 3;
-static long
-extract_reg (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
-{
- int regno;
- long value;
+ /* Extend the sign. */
+ int signbit = 1 << (6 - 1);
+ value = (value ^ signbit) - signbit;
- /* Get the register number. */
- regno = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
+ return value;
+}
- /* Is it a constant marker? */
- if (regno == ARC_REG_SHIMM)
- {
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
- flagshimm_handled_p = 1;
- }
- else if (regno == ARC_REG_SHIMM_UPDATE)
- {
- value = insn[0] & 511;
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (value & 256))
- value -= 512;
- flag_p = 1;
- flagshimm_handled_p = 1;
- }
- else if (regno == ARC_REG_LIMM)
+/* ARC NPS400 Support: See comment near head of file. */
+static unsigned
+insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
{
- value = insn[1];
- limm_p = 1;
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 24;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 24;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
}
- /* It's a register, set OPVAL (that's the only way we distinguish registers
- from constants here). */
+ return insn;
+}
+
+static int
+extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 24) & 0x07;
+ if (value > 3)
+ return (value + 8);
else
- {
- const struct arc_operand_value *reg = lookup_register (REG, regno);
+ return value;
+}
- if (!reg)
- abort ();
- if (opval)
- *opval = reg;
- value = regno;
+static unsigned
+insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ switch (value)
+ {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ insn |= value << 21;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ insn |= (value - 8) << 21;
+ break;
+ default:
+ *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ break;
}
+ return insn;
+}
- /* If this field takes an auxiliary register, see if it's a known one. */
- if ((mods & ARC_MOD_AUXREG)
- && ARC_REG_CONSTANT_P (regno))
- {
- const struct arc_operand_value *reg = lookup_register (AUXREG, value);
+static int
+extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 21) & 0x07;
+ if (value > 3)
+ return (value + 8);
+ else
+ return value;
+}
- /* This is really a constant, but tell the caller it has a special
- name. */
- if (reg && opval)
- *opval = reg;
+static unsigned
+insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ int value ATTRIBUTE_UNUSED,
+ const char **errmsg ATTRIBUTE_UNUSED)
+{
+ if (value < 1 || value > 32)
+ {
+ *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
+ return insn;
}
- return value;
+ --value;
+ insn |= ((value & 0x1f) << 10);
+ return insn;
+}
+
+static int
+extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 10) & 0x1f) + 1;
}
-/* Return the value of the "flag update" field for shimm insns.
- This value is actually stored in the register field. */
+/* Include the generic extract/insert functions. Order is important
+ as some of the functions present in the .h may be disabled via
+ defines. */
+#include "arc-fxi.h"
+
+/* The flag operands table.
-static long
-extract_flag (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ The format of the table is
+ NAME CODE BITS SHIFT FAVAIL. */
+const struct arc_flag_operand arc_flag_operands[] =
{
- int f;
- const struct arc_operand_value *val;
+#define F_NULL 0
+ { 0, 0, 0, 0, 0},
+#define F_ALWAYS (F_NULL + 1)
+ { "al", 0, 0, 0, 0 },
+#define F_RA (F_ALWAYS + 1)
+ { "ra", 0, 0, 0, 0 },
+#define F_EQUAL (F_RA + 1)
+ { "eq", 1, 5, 0, 1 },
+#define F_ZERO (F_EQUAL + 1)
+ { "z", 1, 5, 0, 0 },
+#define F_NOTEQUAL (F_ZERO + 1)
+ { "ne", 2, 5, 0, 1 },
+#define F_NOTZERO (F_NOTEQUAL + 1)
+ { "nz", 2, 5, 0, 0 },
+#define F_POZITIVE (F_NOTZERO + 1)
+ { "p", 3, 5, 0, 1 },
+#define F_PL (F_POZITIVE + 1)
+ { "pl", 3, 5, 0, 0 },
+#define F_NEGATIVE (F_PL + 1)
+ { "n", 4, 5, 0, 1 },
+#define F_MINUS (F_NEGATIVE + 1)
+ { "mi", 4, 5, 0, 0 },
+#define F_CARRY (F_MINUS + 1)
+ { "c", 5, 5, 0, 1 },
+#define F_CARRYSET (F_CARRY + 1)
+ { "cs", 5, 5, 0, 0 },
+#define F_LOWER (F_CARRYSET + 1)
+ { "lo", 5, 5, 0, 0 },
+#define F_CARRYCLR (F_LOWER + 1)
+ { "cc", 6, 5, 0, 0 },
+#define F_NOTCARRY (F_CARRYCLR + 1)
+ { "nc", 6, 5, 0, 1 },
+#define F_HIGHER (F_NOTCARRY + 1)
+ { "hs", 6, 5, 0, 0 },
+#define F_OVERFLOWSET (F_HIGHER + 1)
+ { "vs", 7, 5, 0, 0 },
+#define F_OVERFLOW (F_OVERFLOWSET + 1)
+ { "v", 7, 5, 0, 1 },
+#define F_NOTOVERFLOW (F_OVERFLOW + 1)
+ { "nv", 8, 5, 0, 1 },
+#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
+ { "vc", 8, 5, 0, 0 },
+#define F_GT (F_OVERFLOWCLR + 1)
+ { "gt", 9, 5, 0, 1 },
+#define F_GE (F_GT + 1)
+ { "ge", 10, 5, 0, 1 },
+#define F_LT (F_GE + 1)
+ { "lt", 11, 5, 0, 1 },
+#define F_LE (F_LT + 1)
+ { "le", 12, 5, 0, 1 },
+#define F_HI (F_LE + 1)
+ { "hi", 13, 5, 0, 1 },
+#define F_LS (F_HI + 1)
+ { "ls", 14, 5, 0, 1 },
+#define F_PNZ (F_LS + 1)
+ { "pnz", 15, 5, 0, 1 },
+
+ /* FLAG. */
+#define F_FLAG (F_PNZ + 1)
+ { "f", 1, 1, 15, 1 },
+#define F_FFAKE (F_FLAG + 1)
+ { "f", 0, 0, 0, 1 },
+
+ /* Delay slot. */
+#define F_ND (F_FFAKE + 1)
+ { "nd", 0, 1, 5, 0 },
+#define F_D (F_ND + 1)
+ { "d", 1, 1, 5, 1 },
+#define F_DFAKE (F_D + 1)
+ { "d", 0, 0, 0, 1 },
+
+ /* Data size. */
+#define F_SIZEB1 (F_DFAKE + 1)
+ { "b", 1, 2, 1, 1 },
+#define F_SIZEB7 (F_SIZEB1 + 1)
+ { "b", 1, 2, 7, 1 },
+#define F_SIZEB17 (F_SIZEB7 + 1)
+ { "b", 1, 2, 17, 1 },
+#define F_SIZEW1 (F_SIZEB17 + 1)
+ { "w", 2, 2, 1, 0 },
+#define F_SIZEW7 (F_SIZEW1 + 1)
+ { "w", 2, 2, 7, 0 },
+#define F_SIZEW17 (F_SIZEW7 + 1)
+ { "w", 2, 2, 17, 0 },
+
+ /* Sign extension. */
+#define F_SIGN6 (F_SIZEW17 + 1)
+ { "x", 1, 1, 6, 1 },
+#define F_SIGN16 (F_SIGN6 + 1)
+ { "x", 1, 1, 16, 1 },
+#define F_SIGNX (F_SIGN16 + 1)
+ { "x", 0, 0, 0, 1 },
+
+ /* Address write-back modes. */
+#define F_A3 (F_SIGNX + 1)
+ { "a", 1, 2, 3, 0 },
+#define F_A9 (F_A3 + 1)
+ { "a", 1, 2, 9, 0 },
+#define F_A22 (F_A9 + 1)
+ { "a", 1, 2, 22, 0 },
+#define F_AW3 (F_A22 + 1)
+ { "aw", 1, 2, 3, 1 },
+#define F_AW9 (F_AW3 + 1)
+ { "aw", 1, 2, 9, 1 },
+#define F_AW22 (F_AW9 + 1)
+ { "aw", 1, 2, 22, 1 },
+#define F_AB3 (F_AW22 + 1)
+ { "ab", 2, 2, 3, 1 },
+#define F_AB9 (F_AB3 + 1)
+ { "ab", 2, 2, 9, 1 },
+#define F_AB22 (F_AB9 + 1)
+ { "ab", 2, 2, 22, 1 },
+#define F_AS3 (F_AB22 + 1)
+ { "as", 3, 2, 3, 1 },
+#define F_AS9 (F_AS3 + 1)
+ { "as", 3, 2, 9, 1 },
+#define F_AS22 (F_AS9 + 1)
+ { "as", 3, 2, 22, 1 },
+#define F_ASFAKE (F_AS22 + 1)
+ { "as", 0, 0, 0, 1 },
+
+ /* Cache bypass. */
+#define F_DI5 (F_ASFAKE + 1)
+ { "di", 1, 1, 5, 1 },
+#define F_DI11 (F_DI5 + 1)
+ { "di", 1, 1, 11, 1 },
+#define F_DI15 (F_DI11 + 1)
+ { "di", 1, 1, 15, 1 },
+
+ /* ARCv2 specific. */
+#define F_NT (F_DI15 + 1)
+ { "nt", 0, 1, 3, 1},
+#define F_T (F_NT + 1)
+ { "t", 1, 1, 3, 1},
+#define F_H1 (F_T + 1)
+ { "h", 2, 2, 1, 1 },
+#define F_H7 (F_H1 + 1)
+ { "h", 2, 2, 7, 1 },
+#define F_H17 (F_H7 + 1)
+ { "h", 2, 2, 17, 1 },
+
+ /* Fake Flags. */
+#define F_NE (F_H17 + 1)
+ { "ne", 0, 0, 0, 1 },
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define F_NPS_CL (F_NE + 1)
+ { "cl", 0, 0, 0, 1 },
+
+#define F_NPS_FLAG (F_NPS_CL + 1)
+ { "f", 1, 1, 20, 1 },
+};
- if (flagshimm_handled_p)
- f = flag_p != 0;
- else
- f = (insn[0] & (1 << operand->shift)) != 0;
+const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
- /* There is no text for zero values. */
- if (f == 0)
- return 0;
+/* Table of the flag classes.
- val = arc_opcode_lookup_suffix (operand, 1);
- if (opval && val)
- *opval = val;
- return val->value;
-}
+ The format of the table is
+ CLASS {FLAG_CODE}. */
+const struct arc_flag_class arc_flag_classes[] =
+{
+#define C_EMPTY 0
+ { F_CLASS_NONE, { F_NULL } },
+
+#define C_CC (C_EMPTY + 1)
+ { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+ F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+
+#define C_AA_ADDR3 (C_CC + 1)
+#define C_AA27 (C_CC + 1)
+ { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
+#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
+#define C_AA21 (C_AA_ADDR3 + 1)
+ { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
+#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
+#define C_AA8 (C_AA_ADDR9 + 1)
+ { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
+
+#define C_F (C_AA_ADDR22 + 1)
+ { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
+#define C_FHARD (C_F + 1)
+ { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
+
+#define C_T (C_FHARD + 1)
+ { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
+#define C_D (C_T + 1)
+ { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
+
+#define C_DHARD (C_D + 1)
+ { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
+
+#define C_DI20 (C_DHARD + 1)
+ { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
+#define C_DI16 (C_DI20 + 1)
+ { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
+#define C_DI26 (C_DI16 + 1)
+ { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
+
+#define C_X25 (C_DI26 + 1)
+ { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
+#define C_X15 (C_X25 + 1)
+ { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
+#define C_XHARD (C_X15 + 1)
+#define C_X (C_X15 + 1)
+ { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
+
+#define C_ZZ13 (C_X + 1)
+ { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
+#define C_ZZ23 (C_ZZ13 + 1)
+ { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
+#define C_ZZ29 (C_ZZ23 + 1)
+ { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
+
+#define C_AS (C_ZZ29 + 1)
+ { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
+
+#define C_NE (C_AS + 1)
+ { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define C_NPS_CL (C_NE + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
+
+#define C_NPS_F (C_NPS_CL + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
+};
-/* Extract the condition code (if it exists).
- If we've seen a shimm value in this insn (meaning that the insn can't have
- a condition code field), then we don't store anything in OPVAL and return
- zero. */
-
-static long
-extract_cond (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
-{
- long cond;
- const struct arc_operand_value *val;
-
- if (flagshimm_handled_p)
- return 0;
-
- cond = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
- val = arc_opcode_lookup_suffix (operand, cond);
-
- /* Ignore NULL values of `val'. Several condition code values are
- reserved for extensions. */
- if (opval && val)
- *opval = val;
- return cond;
-}
+/* The operands table.
-/* Extract a branch address.
- We return the value as a real address (not right shifted by 2). */
+ The format of the operands table is:
-static long
-extract_reladdr (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
+ BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
+const struct arc_operand arc_operands[] =
{
- long addr;
+ /* The fields are bits, shift, insert, extract, flags. The zero
+ index is used to indicate end-of-list. */
+#define UNUSED 0
+ { 0, 0, 0, 0, 0, 0 },
+ /* The plain integer register fields. Used by 32 bit
+ instructions. */
+#define RA (UNUSED + 1)
+ { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
+#define RB (RA + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
+#define RC (RB + 1)
+ { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
+#define RBdup (RC + 1)
+ { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
+
+#define RAD (RBdup + 1)
+ { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RCD (RAD + 1)
+ { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
+
+ /* The plain integer register fields. Used by short
+ instructions. */
+#define RA16 (RCD + 1)
+#define RA_S (RCD + 1)
+ { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
+#define RB16 (RA16 + 1)
+#define RB_S (RA16 + 1)
+ { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
+#define RB16dup (RB16 + 1)
+#define RB_Sdup (RB16 + 1)
+ { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
+#define RC16 (RB16dup + 1)
+#define RC_S (RB16dup + 1)
+ { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
+#define R6H (RC16 + 1) /* 6bit register field 'h' used
+ by V1 cpus. */
+ { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
+#define R5H (R6H + 1) /* 5bit register field 'h' used
+ by V2 cpus. */
+#define RH_S (R6H + 1) /* 5bit register field 'h' used
+ by V2 cpus. */
+ { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
+#define R5Hdup (R5H + 1)
+#define RH_Sdup (R5H + 1)
+ { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
+ insert_rhv2, extract_rhv2 },
+
+#define RG (R5Hdup + 1)
+#define G_S (R5Hdup + 1)
+ { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
+
+ /* Fix registers. */
+#define R0 (RG + 1)
+#define R0_S (RG + 1)
+ { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
+#define R1 (R0 + 1)
+#define R1_S (R0 + 1)
+ { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
+#define R2 (R1 + 1)
+#define R2_S (R1 + 1)
+ { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
+#define R3 (R2 + 1)
+#define R3_S (R2 + 1)
+ { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
+#define SP (R3 + 1)
+#define SP_S (R3 + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
+#define SPdup (SP + 1)
+#define SP_Sdup (SP + 1)
+ { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
+#define GP (SPdup + 1)
+#define GP_S (SPdup + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
+
+#define PCL_S (GP + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
+
+#define BLINK (PCL_S + 1)
+#define BLINK_S (PCL_S + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
+
+#define ILINK1 (BLINK + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
+#define ILINK2 (ILINK1 + 1)
+ { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
+
+ /* Long immediate. */
+#define LIMM (ILINK2 + 1)
+#define LIMM_S (ILINK2 + 1)
+ { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
+#define LIMMdup (LIMM + 1)
+ { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
+
+ /* Special operands. */
+#define ZA (LIMMdup + 1)
+#define ZB (LIMMdup + 1)
+#define ZA_S (LIMMdup + 1)
+#define ZB_S (LIMMdup + 1)
+#define ZC_S (LIMMdup + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
+
+#define RRANGE_EL (ZA + 1)
+ { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
+ insert_rrange, extract_rrange},
+#define FP_EL (RRANGE_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_fpel, extract_fpel },
+#define BLINK_EL (FP_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_blinkel, extract_blinkel },
+#define PCL_EL (BLINK_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_pclel, extract_pclel },
+
+ /* Fake operand to handle the T flag. */
+#define BRAKET (PCL_EL + 1)
+#define BRAKETdup (PCL_EL + 1)
+ { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
+
+ /* Fake operand to handle the T flag. */
+#define FKT_T (BRAKET + 1)
+ { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
+ /* Fake operand to handle the T flag. */
+#define FKT_NT (FKT_T + 1)
+ { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
+
+ /* UIMM6_20 mask = 00000000000000000000111111000000. */
+#define UIMM6_20 (FKT_NT + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
+
+ /* SIMM12_20 mask = 00000000000000000000111111222222. */
+#define SIMM12_20 (UIMM6_20 + 1)
+ {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
+
+ /* SIMM3_5_S mask = 0000011100000000. */
+#define SIMM3_5_S (SIMM12_20 + 1)
+ {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
+ insert_simm3s, extract_simm3s},
+
+ /* UIMM7_A32_11_S mask = 0000000000011111. */
+#define UIMM7_A32_11_S (SIMM3_5_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
+ extract_uimm7_a32_11_s},
+
+ /* UIMM7_9_S mask = 0000000001111111. */
+#define UIMM7_9_S (UIMM7_A32_11_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
+
+ /* UIMM3_13_S mask = 0000000000000111. */
+#define UIMM3_13_S (UIMM7_9_S + 1)
+ {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
+
+ /* SIMM11_A32_7_S mask = 0000000111111111. */
+#define SIMM11_A32_7_S (UIMM3_13_S + 1)
+ {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
+
+ /* UIMM6_13_S mask = 0000000002220111. */
+#define UIMM6_13_S (SIMM11_A32_7_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
+ /* UIMM5_11_S mask = 0000000000011111. */
+#define UIMM5_11_S (UIMM6_13_S + 1)
+ {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
+ extract_uimm5_11_s},
+
+ /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
+#define SIMM9_A16_8 (UIMM5_11_S + 1)
+ {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
+ extract_simm9_a16_8},
+
+ /* UIMM6_8 mask = 00000000000000000000111111000000. */
+#define UIMM6_8 (SIMM9_A16_8 + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
+
+ /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
+#define SIMM21_A16_5 (UIMM6_8 + 1)
+ {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
+ insert_simm21_a16_5, extract_simm21_a16_5},
+
+ /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
+#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
+ {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
+ insert_simm25_a16_5, extract_simm25_a16_5},
+
+ /* SIMM10_A16_7_S mask = 0000000111111111. */
+#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
+ {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
+ extract_simm10_a16_7_s},
+
+#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
+ {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
+
+ /* SIMM7_A16_10_S mask = 0000000000111111. */
+#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
+ {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
+ extract_simm7_a16_10_s},
+
+ /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
+#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
+ {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
+ extract_simm21_a32_5},
+
+ /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
+#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
+ {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
+ extract_simm25_a32_5},
+
+ /* SIMM13_A32_5_S mask = 0000011111111111. */
+#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
+ {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
+ extract_simm13_a32_5_s},
+
+ /* SIMM8_A16_9_S mask = 0000000001111111. */
+#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
+ {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
+ extract_simm8_a16_9_s},
+
+ /* UIMM3_23 mask = 00000000000000000000000111000000. */
+#define UIMM3_23 (SIMM8_A16_9_S + 1)
+ {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
+
+ /* UIMM10_6_S mask = 0000001111111111. */
+#define UIMM10_6_S (UIMM3_23 + 1)
+ {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
+
+ /* UIMM6_11_S mask = 0000002200011110. */
+#define UIMM6_11_S (UIMM10_6_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
+
+ /* SIMM9_8 mask = 00000000111111112000000000000000. */
+#define SIMM9_8 (UIMM6_11_S + 1)
+ {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
+ insert_simm9_8, extract_simm9_8},
+
+ /* UIMM10_A32_8_S mask = 0000000011111111. */
+#define UIMM10_A32_8_S (SIMM9_8 + 1)
+ {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
+ extract_uimm10_a32_8_s},
+
+ /* SIMM9_7_S mask = 0000000111111111. */
+#define SIMM9_7_S (UIMM10_A32_8_S + 1)
+ {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
+ extract_simm9_7_s},
+
+ /* UIMM6_A16_11_S mask = 0000000000011111. */
+#define UIMM6_A16_11_S (SIMM9_7_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
+ extract_uimm6_a16_11_s},
+
+ /* UIMM5_A32_11_S mask = 0000020000011000. */
+#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
+ {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
+ extract_uimm5_a32_11_s},
+
+ /* SIMM11_A32_13_S mask = 0000022222200111. */
+#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
+ {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
+
+ /* UIMM7_13_S mask = 0000000022220111. */
+#define UIMM7_13_S (SIMM11_A32_13_S + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
+
+ /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
+#define UIMM6_A16_21 (UIMM7_13_S + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
+
+ /* UIMM7_11_S mask = 0000022200011110. */
+#define UIMM7_11_S (UIMM6_A16_21 + 1)
+ {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
+
+ /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
+#define UIMM7_A16_20 (UIMM7_11_S + 1)
+ {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
+ extract_uimm7_a16_20},
+
+ /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
+#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
+ {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
+ extract_simm13_a16_20},
+
+ /* UIMM8_8_S mask = 0000000011111111. */
+#define UIMM8_8_S (SIMM13_A16_20 + 1)
+ {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
+
+ /* W6 mask = 00000000000000000000111111000000. */
+#define W6 (UIMM8_8_S + 1)
+ {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
+
+ /* UIMM6_5_S mask = 0000011111100000. */
+#define UIMM6_5_S (W6 + 1)
+ {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
+
+ /* ARC NPS400 Support: See comment near head of file. */
+#define NPS_R_DST_3B (UIMM6_5_S + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+
+#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+
+#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
+
+#define NPS_R_DST (NPS_R_SRC2_3B + 1)
+ { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, NULL, NULL },
+
+#define NPS_R_SRC1 (NPS_R_DST + 1)
+ { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, NULL, NULL },
+
+#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
+
+#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_size, extract_nps_bitop_size },
+
+#define NPS_UIMM16 (NPS_BITOP_SIZE + 1)
+ { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+};
- addr = (insn[0] >> operand->shift) & ((1 << operand->bits) - 1);
- if ((operand->flags & ARC_OPERAND_SIGNED)
- && (addr & (1 << (operand->bits - 1))))
- addr -= 1 << operand->bits;
+const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
- return addr << 2;
-}
+const unsigned arc_Toperand = FKT_T;
+const unsigned arc_NToperand = FKT_NT;
-/* The only thing this does is set the `invalid' flag if B != C.
- This is needed because the "mov" macro appears before it's real insn "and"
- and we don't want the disassembler to confuse them. */
-
-static long
-extract_unopmacro (insn, operand, mods, opval, invalid)
- arc_insn *insn;
- const struct arc_operand *operand;
- int mods;
- const struct arc_operand_value **opval;
- int *invalid;
-{
- /* ??? This misses the case where B == ARC_REG_SHIMM_UPDATE &&
- C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
- printed as "and"s. */
- if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
- != ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
- if (invalid)
- *invalid = 1;
+/* The opcode table.
- return 0;
-}
+ The format of the opcode table is:
-/* Utility for the extraction functions to return the index into
- `arc_suffixes'. */
+ NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }. */
+const struct arc_opcode arc_opcodes[] =
+{
+#include "arc-tbl.h"
+#include "arc-nps400-tbl.h"
+#include "arc-ext-tbl.h"
+};
-const struct arc_operand_value *
-arc_opcode_lookup_suffix (type, value)
- const struct arc_operand *type;
- int value;
+const unsigned arc_num_opcodes = ARRAY_SIZE (arc_opcodes);
+
+/* List with special cases instructions and the applicable flags. */
+const struct arc_flag_special arc_flag_special_cases[] =
{
- register const struct arc_operand_value *v,*end;
+ { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
+ F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
+ { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
+};
- /* ??? This is a little slow and can be speeded up. */
+const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
- for (v = arc_suffixes, end = arc_suffixes + arc_suffixes_count; v < end; ++v)
- if (type == &arc_operands[v->type]
- && value == v->value)
- return v;
- return 0;
-}
+/* Relocations. */
+const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
+{
+ { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+ { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
+
+ /* Next two entries will cover the undefined behavior ldb/stb with
+ address scaling. */
+ { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+ { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
+
+ { "sda", "ld", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "st", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+ { "sda", "ldd", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
+ { "sda", "std", { F_ASFAKE, F_NULL },
+ BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
+
+ /* Short instructions. */
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
+ { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
+
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
+ { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
+ BFD_RELOC_ARC_S25H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
+ BFD_RELOC_ARC_S21H_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
+ BFD_RELOC_ARC_S25W_PCREL_PLT },
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
+ BFD_RELOC_ARC_S21W_PCREL_PLT },
+
+ { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
+};
-static const struct arc_operand_value *
-lookup_register (type, regno)
- int type;
- long regno;
+const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
+
+const struct arc_pseudo_insn arc_pseudo_insns[] =
{
- register const struct arc_operand_value *r,*end;
+ { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+ { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
+ { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
+ { BRAKETdup, 1, 0, 4} } },
+
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+ { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
+ { SIMM9_A16_8, 0, 0, 2 } } },
+};
+
+const unsigned arc_num_pseudo_insn =
+ sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
- if (type == REG)
- return &arc_reg_names[regno];
+const struct arc_aux_reg arc_aux_regs[] =
+{
+#undef DEF
+#define DEF(ADDR, NAME) \
+ { ADDR, #NAME, sizeof (#NAME)-1 },
- /* ??? This is a little slow and can be speeded up. */
+#include "arc-regs.h"
- for (r = arc_reg_names, end = arc_reg_names + arc_reg_names_count;
- r < end; ++r)
- if (type == r->type && regno == r->value)
- return r;
- return 0;
-}
+#undef DEF
+};
+
+const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
+
+/* NOTE: The order of this array MUST be consistent with 'enum
+ arc_rlx_types' located in tc-arc.h! */
+const struct arc_opcode arc_relax_opcodes[] =
+{
+ { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
+
+ /* bl_s s13 11111sssssssssss. */
+ { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM13_A32_5_S }, { 0 }},
+
+ /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
+ { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A32_5 }, { C_D }},
+
+ /* b_s s10 1111000sssssssss. */
+ { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM10_A16_7_S }, { 0 }},
+
+ /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
+ { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
+ { SIMM25_A16_5 }, { C_D }},
+
+ /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
+ { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+ /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
+ UIMM6_20_PCREL. */
+ { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20 }, { C_F }},
+
+ /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
+ { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
+ { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,s9
+ 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
+ { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
+ { C_ZZ23, C_DI20, C_AA21, C_X25 }},
+
+ /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
+ { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RA, BRAKET, RB, LIMM, BRAKETdup },
+ { C_ZZ13, C_DI16, C_AA8, C_X15 }},
+
+ /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
+ { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB_S, UIMM8_8_S }, { 0 }},
+
+ /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
+ SIMM12_20_PCREL. */
+ { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, SIMM12_20 }, { C_F }},
+
+ /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
+ { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F }},
+
+ /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
+ { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+
+ /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
+ UIMM6_20_PCREL. */
+ { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, UIMM6_20 }, { C_F }},
+
+ /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
+ { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RA, RB, LIMM }, { C_F }},
+
+ /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
+ UIMM6_20_PCREL. */
+ { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+
+ /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
+ { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
+
+ /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
+ UIMM6_20_PCREL. */
+ { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, UIMM6_20 }, { C_F, C_CC }},
+
+ /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
+ { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
+ { RB, LIMM }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
+ UIMM6_20_PCREL. */
+ { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+
+ /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
+ { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
+ | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
+ { RB, RBdup, LIMM }, { C_F, C_CC }}
+};
+
+const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
projects / deliverable / binutils-gdb.git / blobdiff