/* Opcode table for the ARC.
- Copyright (C) 1994-2019 Free Software Foundation, Inc.
+ Copyright (C) 1994-2020 Free Software Foundation, Inc.
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
{ F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
#define C_NE (C_AS + 1)
- { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NE, F_NULL}},
/* ARC NPS400 Support: See comment near head of file. */
#define C_NPS_CL (C_NE + 1)
#define RAD (RBdup + 1)
{ 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RCD (RAD + 1)
+#define RAD_CHK (RAD + 1)
+ { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RCD (RAD_CHK + 1)
{ 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
/* The plain integer register fields. Used by short