/* Opcode table for the ARC.
- Copyright 1994, 1995 Free Software Foundation, Inc.
+ Copyright (c) 1994, 1995, 1997, 1998 Free Software Foundation, Inc.
Contributed by Doug Evans (dje@cygnus.com).
This program is free software; you can redistribute it and/or modify
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
-#include "ansidecl.h"
+#include <stdio.h>
+#include "sysdep.h"
#include "opcode/arc.h"
+#include "opintl.h"
+
+#ifndef NULL
+#define NULL 0
+#endif
#define INSERT_FN(fn) \
static arc_insn fn PARAMS ((arc_insn, const struct arc_operand *, \
INSERT_FN (insert_reladdr);
INSERT_FN (insert_absaddr);
INSERT_FN (insert_unopmacro);
-INSERT_FN (insert_multshift);
EXTRACT_FN (extract_reg);
EXTRACT_FN (extract_flag);
EXTRACT_FN (extract_cond);
EXTRACT_FN (extract_reladdr);
EXTRACT_FN (extract_unopmacro);
-EXTRACT_FN (extract_multshift);
/* Various types of ARC operands, including insn suffixes. */
'e' CACHEBYPASS5 cache bypass in ld a,[b,c]
'E' CACHEBYPASS14 cache bypass in ld a,[b,shimm]
'D' CACHEBYPASS26 cache bypass in st c,[b,shimm]
- 'u' UNSIGNED unsigned multiply
- 's' SATURATION saturation limit in audio arc mac insn
'U' UNOPMACRO fake operand to copy REGB to REGC for unop macros
The following modifiers may appear between the % and char (eg: %.f):
/* register A or shimm/limm indicator */
#define REGA (UNUSED + 1)
- { 'a', 6, ARC_SHIFT_REGA, 0, insert_reg, extract_reg },
+ { 'a', 6, ARC_SHIFT_REGA, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* register B or shimm/limm indicator */
#define REGB (REGA + 1)
- { 'b', 6, ARC_SHIFT_REGB, 0, insert_reg, extract_reg },
+ { 'b', 6, ARC_SHIFT_REGB, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* register C or shimm/limm indicator */
#define REGC (REGB + 1)
- { 'c', 6, ARC_SHIFT_REGC, 0, insert_reg, extract_reg },
+ { 'c', 6, ARC_SHIFT_REGC, ARC_OPERAND_SIGNED, insert_reg, extract_reg },
/* fake operand used to insert shimm value into most instructions */
#define SHIMMFINISH (REGC + 1)
{ 'S', 9, 0, ARC_OPERAND_SIGNED + ARC_OPERAND_FAKE, insert_shimmfinish, 0 },
-/* fake operand used to insert limm value into most instructions;
- this is also used for .word handling */
+/* fake operand used to insert limm value into most instructions. */
#define LIMMFINISH (SHIMMFINISH + 1)
{ 'L', 32, 32, ARC_OPERAND_ADDRESS + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_limmfinish, 0 },
{ 'B', 20, 7, ARC_OPERAND_RELATIVE_BRANCH + ARC_OPERAND_SIGNED, insert_reladdr, extract_reladdr },
/* jump address; j insn (this is basically the same as 'L' except that the
- value is right shifted by 2); this is also used for .word handling */
+ value is right shifted by 2) */
#define JUMP (BRANCH + 1)
{ 'J', 24, 32, ARC_OPERAND_ABSOLUTE_BRANCH + ARC_OPERAND_LIMM + ARC_OPERAND_FAKE, insert_absaddr },
#define CACHEBYPASS26 (CACHEBYPASS14 + 1)
{ 'D', 1, 26, ARC_OPERAND_SUFFIX },
-/* unsigned multiply */
-#define UNSIGNED (CACHEBYPASS26 + 1)
- { 'u', 1, 27, ARC_OPERAND_SUFFIX },
-
-/* unsigned multiply */
-#define SATURATION (UNSIGNED + 1)
- { 's', 1, 28, ARC_OPERAND_SUFFIX },
-
/* unop macro, used to copy REGB to REGC */
-#define UNOPMACRO (SATURATION + 1)
+#define UNOPMACRO (CACHEBYPASS26 + 1)
{ 'U', 6, ARC_SHIFT_REGC, ARC_OPERAND_FAKE, insert_unopmacro, extract_unopmacro },
/* '.' modifier ('.' required). */
#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC)
#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */
-/* ARC instructions (sorted by at least the first letter, and equivalent
- opcodes kept together).
-
- By recording the insns this way, the table is not hashable on the opcode.
- That's not a real loss though as there are only a few entries for each
- insn (ld/st being the exception), which are quickly found and since
- they're stored together (eg: all `ld' variants are together) very little
- time is spent on the opcode itself. The slow part is parsing the options,
- but that's always going to be slow.
+/* ARC instructions.
Longer versions of insns must appear before shorter ones (if gas sees
"lsr r2,r3,1" when it's parsing "lsr %a,%b" it will think the ",1" is
- junk).
+ junk). This isn't necessary for `ld' because of the trailing ']'.
- This table is best viewed on a wide screen (161 columns).
- I'd prefer to keep it this way. */
+ Instructions that are really macros based on other insns must appear
+ before the real insn so they're chosen when disassembling. Eg: The `mov'
+ insn is really the `and' insn.
+
+ This table is best viewed on a wide screen (161 columns). I'd prefer to
+ keep it this way. The rest of the file, however, should be viewable on an
+ 80 column terminal. */
/* ??? This table also includes macros: asl, lsl, and mov. The ppc port has
a more general facility for dealing with macros which could be used if
we need to. */
-/* ??? As an experiment, the "mov" macro appears at the start so it is
- prefered to "and" when disassembling. At present, the table needn't be
- sorted, though all opcodes with the same first letter must be kept
- together. */
-
-const struct arc_opcode arc_opcodes[] = {
- { "mac%u%.s%.q%.f %a,%b,%c%F%S%L", I(-4), I(24), ARC_MACH_AUDIO },
- /* Note that "mov" is really an "and". */
+
+/* This table can't be `const' because members `next_asm' and `next_dis' are
+ computed at run-time. We could split this into two, but that doesn't seem
+ worth it. */
+
+struct arc_opcode arc_opcodes[] = {
+
+ /* Macros appear first. */
+ /* "mov" is really an "and". */
{ "mov%.q%.f %a,%b%F%S%L%U", I(-1), I(12) },
- { "mul%u%.q%.f %a,%b,%c%F%S%L", I(-2), I(28), ARC_MACH_AUDIO },
- /* ??? This insn allows an optional "0," preceding the args. */
- /* We can't use %u here because it's not a suffix (the "64" is in the way). */
- { "mul64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(20)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- { "mulu64%.q%.f %b,%c%F%S%L", I(-1)+A(-1), I(21)+A(-1), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
+ /* "asl" is really an "add". */
+ { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ /* "lsl" is really an "add". */
+ { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
+ /* "nop" is really an "xor". */
+ { "nop", 0xffffffff, 0x7fffffff },
+ /* "rlc" is really an "adc". */
+ { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
+ /* The rest of these needn't be sorted, but it helps to find them if they are. */
{ "adc%.q%.f %a,%b,%c%F%S%L", I(-1), I(9) },
{ "add%.q%.f %a,%b,%c%F%S%L", I(-1), I(8) },
{ "and%.q%.f %a,%b,%c%F%S%L", I(-1), I(12) },
- { "asl%.q%.f %a,%b,%c%F%S%L", I(-1), I(16), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
- /* Note that "asl" is really an "add". */
- { "asl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "asr%.q%.f %a,%b,%c%F%S%L", I(-1), I(18), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
{ "asr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(1) },
{ "bic%.q%.f %a,%b,%c%F%S%L", I(-1), I(14) },
- { "b%q%.n %B", I(-1), I(4) },
- { "bl%q%.n %B", I(-1), I(5) },
+ { "b%q%.n %B", I(-1), I(4), ARC_OPCODE_COND_BRANCH },
+ { "bl%q%.n %B", I(-1), I(5), ARC_OPCODE_COND_BRANCH },
{ "extb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(7) },
{ "extw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(8) },
{ "flag%.q %b%G%S%L", I(-1)+A(-1)+C(-1), I(3)+A(ARC_REG_SHIMM_UPDATE)+C(0) },
/* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
{ "ld%Z%.X%.W%.E %0%a,[%b]%L", I(-1)+R(-1,13,1)+R(-1,0,511), I(1)+R(0,13,1)+R(0,0,511) },
{ "ld%Z%.X%.W%.E %a,[%b,%d]%S%L", I(-1)+R(-1,13,1), I(1)+R(0,13,1) },
- { "ld%z%.x%.w%.e %a,[%b,%c]", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
+ { "ld%z%.x%.w%.e%Q %a,[%b,%c]%L", I(-1)+R(-1,4,1)+R(-1,6,7), I(0)+R(0,4,1)+R(0,6,7) },
{ "lp%q%.n %B", I(-1), I(6), },
{ "lr %a,[%Ab]%S%L", I(-1)+C(-1), I(1)+C(0x10) },
- /* Note that "lsl" is really an "add". */
- { "lsl%.q%.f %a,%b%F%S%L%U", I(-1), I(8) },
- { "lsr%.q%.f %a,%b,%c%F%S%L", I(-1), I(17), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
{ "lsr%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(2) },
- /* Note that "nop" is really an "xor". */
- { "nop", 0xffffffff, 0x7fffffff },
{ "or%.q%.f %a,%b,%c%F%S%L", I(-1), I(13) },
- /* ??? The %a here should be %p or something. */
- { "padc%.q%.f %a,%b,%c%F%S%L", I(-1), I(25), ARC_MACH_GRAPHICS },
- { "padd%.q%.f %a,%b,%c%F%S%L", I(-1), I(24), ARC_MACH_GRAPHICS },
- /* Note that "pmov" is really a "pand". */
- { "pmov%.q%.f %a,%b%F%S%L%U", I(-1), I(28), ARC_MACH_GRAPHICS },
- { "pand%.q%.f %a,%b,%c%F%S%L", I(-1), I(28), ARC_MACH_GRAPHICS },
- { "psbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(27), ARC_MACH_GRAPHICS },
- { "psub%.q%.f %a,%b,%c%F%S%L", I(-1), I(26), ARC_MACH_GRAPHICS },
- /* Note that "rlc" is really an "adc". */
- { "rlc%.q%.f %a,%b%F%S%L%U", I(-1), I(9) },
- { "ror%.q%.f %a,%b,%c%F%S%L", I(-1), I(19), ARC_MACH_HOST+ARC_MACH_GRAPHICS },
{ "ror%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(3) },
{ "rrc%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(4) },
{ "sbc%.q%.f %a,%b,%c%F%S%L", I(-1), I(11) },
{ "sexb%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(5) },
{ "sexw%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(6) },
- { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
+ { "sr %c,[%Ab]%S%L", I(-1)+A(-1), I(2)+A(0x10) },
/* "[%b]" is before "[%b,%d]" so 0 offsets don't get printed. */
- { "st%y%.v%.D %0%c,[%b]%L", I(-1)+R(-1,25,3)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,3)+R(0,21,1)+R(0,0,511) },
- { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,3)+R(-1,21,1), I(2)+R(0,25,3)+R(0,21,1) },
+ { "st%y%.v%.D%Q %0%c,[%b]%L", I(-1)+R(-1,25,1)+R(-1,21,1)+R(-1,0,511), I(2)+R(0,25,1)+R(0,21,1)+R(0,0,511) },
+ { "st%y%.v%.D %c,[%b,%d]%S%L", I(-1)+R(-1,25,1)+R(-1,21,1), I(2)+R(0,25,1)+R(0,21,1) },
{ "sub%.q%.f %a,%b,%c%F%S%L", I(-1), I(10) },
- { "swap%.q%.f %a,%b%F%S%L", I(-1)+C(-1), I(3)+C(9), ARC_MACH_AUDIO },
{ "xor%.q%.f %a,%b,%c%F%S%L", I(-1), I(15) }
};
const int arc_opcodes_count = sizeof (arc_opcodes) / sizeof (arc_opcodes[0]);
to recognize the canonical values. */
{ "r27", 27, REG }, { "r28", 28, REG },
+ /* Someone may wish to refer to these in this way, and it's probably a
+ good idea to reserve them as such anyway. */
+ { "r29", 29, REG }, { "r30", 30, REG }, { "r31", 31, REG }, { "r60", 60, REG },
+
/* Standard auxiliary registers. */
{ "status", 0, AUXREG },
{ "semaphore", 1, AUXREG },
{ "lp_end", 3, AUXREG },
{ "identity", 4, AUXREG },
{ "debug", 5, AUXREG },
-
- /* Host ARC Extensions. */
- { "mlo", 57, REG, ARC_MACH_HOST },
- { "mmid", 58, REG, ARC_MACH_HOST },
- { "mhi", 59, REG, ARC_MACH_HOST },
- { "ivic", 0x10, AUXREG, ARC_MACH_HOST },
- { "ivdc", 0x11, AUXREG, ARC_MACH_HOST },
- { "ivdcn", 0x12, AUXREG, ARC_MACH_HOST },
- { "flushd", 0x13, AUXREG, ARC_MACH_HOST },
- { "saha", 0x14, AUXREG, ARC_MACH_HOST },
- { "gahd", 0x15, AUXREG, ARC_MACH_HOST },
- { "aahd", 0x16, AUXREG, ARC_MACH_HOST },
- { "rrcr", 0x17, AUXREG, ARC_MACH_HOST },
- { "rpcr", 0x18, AUXREG, ARC_MACH_HOST },
- { "flushdn", 0x19, AUXREG, ARC_MACH_HOST },
- { "dbgad1", 0x1a, AUXREG, ARC_MACH_HOST },
- { "dbgad2", 0x1b, AUXREG, ARC_MACH_HOST },
- { "dbgmde", 0x1c, AUXREG, ARC_MACH_HOST },
- { "dbgstat", 0x1d, AUXREG, ARC_MACH_HOST },
- { "wag", 0x1e, AUXREG, ARC_MACH_HOST },
- { "mulhi", 0x1f, AUXREG, ARC_MACH_HOST },
- { "intwide", 0x20, AUXREG, ARC_MACH_HOST },
- { "intgen", 0x21, AUXREG, ARC_MACH_HOST },
- { "rfsh_n", 0x22, AUXREG, ARC_MACH_HOST },
-
- /* Graphics ARC Extensions. */
- { "mlo", 57, REG, ARC_MACH_GRAPHICS },
- { "mmid", 58, REG, ARC_MACH_GRAPHICS },
- { "mhi", 59, REG, ARC_MACH_GRAPHICS },
- { "ivic", 0x10, AUXREG, ARC_MACH_GRAPHICS },
- { "wag", 0x1e, AUXREG, ARC_MACH_GRAPHICS },
- { "mulhi", 0x1f, AUXREG, ARC_MACH_GRAPHICS },
- { "intwide", 0x20, AUXREG, ARC_MACH_GRAPHICS },
- { "intgen", 0x21, AUXREG, ARC_MACH_GRAPHICS },
- { "pix", 0x100, AUXREG, ARC_MACH_GRAPHICS },
- { "scratch", 0x120, AUXREG, ARC_MACH_GRAPHICS },
-
- /* Audio ARC Extensions. */
- { "macmode", 39, REG, ARC_MACH_AUDIO },
- { "rs1", 40, REG, ARC_MACH_AUDIO },
- { "rs1n", 41, REG, ARC_MACH_AUDIO },
- { "rs1start", 42, REG, ARC_MACH_AUDIO },
- { "rs1size", 43, REG, ARC_MACH_AUDIO },
- { "rs1delta", 44, REG, ARC_MACH_AUDIO },
- { "rs1pos", 45, REG, ARC_MACH_AUDIO },
- { "rd1", 46, REG, ARC_MACH_AUDIO },
- { "rd1n", 47, REG, ARC_MACH_AUDIO },
- { "rd1d", 48, REG, ARC_MACH_AUDIO },
- { "rd1pos", 49, REG, ARC_MACH_AUDIO },
- { "rs2", 50, REG, ARC_MACH_AUDIO },
- { "rs2n", 51, REG, ARC_MACH_AUDIO },
- { "rs2start", 52, REG, ARC_MACH_AUDIO },
- { "rs2size", 53, REG, ARC_MACH_AUDIO },
- { "rs2delta", 54, REG, ARC_MACH_AUDIO },
- { "rs2pos", 55, REG, ARC_MACH_AUDIO },
- { "rd2", 56, REG, ARC_MACH_AUDIO },
- { "rd2n", 57, REG, ARC_MACH_AUDIO },
- { "rd2d", 58, REG, ARC_MACH_AUDIO },
- { "rd2pos", 59, REG, ARC_MACH_AUDIO },
- { "ivic", 0x10, AUXREG, ARC_MACH_AUDIO },
- { "wag", 0x1e, AUXREG, ARC_MACH_AUDIO },
- { "intwide", 0x20, AUXREG, ARC_MACH_AUDIO },
- { "intgen", 0x21, AUXREG, ARC_MACH_AUDIO },
- { "bm_sstart", 0x30, AUXREG, ARC_MACH_AUDIO },
- { "bm_length", 0x31, AUXREG, ARC_MACH_AUDIO },
- { "bm_rstart", 0x32, AUXREG, ARC_MACH_AUDIO },
- { "bm_go", 0x33, AUXREG, ARC_MACH_AUDIO },
- { "xtp_newval", 0x40, AUXREG, ARC_MACH_AUDIO },
- { "sram", 0x400, AUXREG, ARC_MACH_AUDIO },
- { "reg_file", 0x800, AUXREG, ARC_MACH_AUDIO },
};
const int arc_reg_names_count = sizeof (arc_reg_names) / sizeof (arc_reg_names[0]);
{ "ls", 14, COND },
{ "pnz", 15, COND },
{ "f", 1, FLAG },
- { "nd", 0, DELAY },
- { "d", 1, DELAY },
- { "jd", 2, DELAY },
+ { "nd", ARC_DELAY_NONE, DELAY },
+ { "d", ARC_DELAY_NORMAL, DELAY },
+ { "jd", ARC_DELAY_JUMP, DELAY },
/*{ "b", 7, SIZEEXT },*/
/*{ "b", 5, SIZESEX },*/
{ "b", 1, SIZE1 },
{ "di", 1, CACHEBYPASS5 },
{ "di", 1, CACHEBYPASS14 },
{ "di", 1, CACHEBYPASS26 },
-
- /* Audio ARC Extensions. */
- /* ??? The values here are guesses. */
- { "ss", 16, COND, ARC_MACH_AUDIO },
- { "sc", 17, COND, ARC_MACH_AUDIO },
- { "mh", 18, COND, ARC_MACH_AUDIO },
- { "ml", 19, COND, ARC_MACH_AUDIO },
};
const int arc_suffixes_count = sizeof (arc_suffixes) / sizeof (arc_suffixes[0]);
+
+/* Indexed by first letter of opcode. Points to chain of opcodes with same
+ first letter. */
+static struct arc_opcode *opcode_map[26 + 1];
+
+/* Indexed by insn code. Points to chain of opcodes with same insn code. */
+static struct arc_opcode *icode_map[32];
\f
/* Configuration flags. */
{
static int mach_type_map[] =
{
- ARC_MACH_BASE, ARC_MACH_HOST, ARC_MACH_GRAPHICS, ARC_MACH_AUDIO
+ ARC_MACH_BASE
};
return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0);
arc_opcode_init_tables (flags)
int flags;
{
- register int i,n;
- static int map_init_p = 0;
+ static int init_p = 0;
cpu_type = flags;
/* We may be intentionally called more than once (for example gdb will call
- us each time the user switches cpu). This table only needs to be init'd
+ us each time the user switches cpu). These tables only need to be init'd
once though. */
- if (!map_init_p)
+ /* ??? We can remove the need for arc_opcode_supported by taking it into
+ account here, but I'm not sure I want to do that yet (if ever). */
+ if (!init_p)
{
+ register int i,n;
+
memset (arc_operand_map, 0, sizeof (arc_operand_map));
n = sizeof (arc_operands) / sizeof (arc_operands[0]);
- for (i = 0; i < n; i++)
+ for (i = 0; i < n; ++i)
arc_operand_map[arc_operands[i].fmt] = i;
- map_init_p = 1;
+
+ memset (opcode_map, 0, sizeof (opcode_map));
+ memset (icode_map, 0, sizeof (icode_map));
+ /* Scan the table backwards so macros appear at the front. */
+ for (i = arc_opcodes_count - 1; i >= 0; --i)
+ {
+ int opcode_hash = ARC_HASH_OPCODE (arc_opcodes[i].syntax);
+ int icode_hash = ARC_HASH_ICODE (arc_opcodes[i].value);
+
+ arc_opcodes[i].next_asm = opcode_map[opcode_hash];
+ opcode_map[opcode_hash] = &arc_opcodes[i];
+
+ arc_opcodes[i].next_dis = icode_map[icode_hash];
+ icode_map[icode_hash] = &arc_opcodes[i];
+ }
+
+ init_p = 1;
}
}
return 1;
return 0;
}
+
+/* Return the first insn in the chain for assembling INSN. */
+
+const struct arc_opcode *
+arc_opcode_lookup_asm (insn)
+ const char *insn;
+{
+ return opcode_map[ARC_HASH_OPCODE (insn)];
+}
+
+/* Return the first insn in the chain for disassembling INSN. */
+
+const struct arc_opcode *
+arc_opcode_lookup_dis (insn)
+ unsigned int insn;
+{
+ return icode_map[ARC_HASH_ICODE (insn)];
+}
\f
/* Nonzero if we've seen an 'f' suffix (in certain insns). */
static int flag_p;
{
static char buf[100];
- if (!reg)
+ if (reg == NULL)
{
/* We have a constant that also requires a value stored in a register
field. Handle these by updating the register field and saving the
}
else
{
- *errmsg = "unable to fit different valued constants into instruction";
+ *errmsg = _("unable to fit different valued constants into instruction");
}
}
else
if (reg->type == AUXREG)
{
if (!(mods & ARC_MOD_AUXREG))
- *errmsg = "auxiliary register not allowed here";
+ *errmsg = _("auxiliary register not allowed here");
else
{
insn |= ARC_REG_SHIMM << operand->shift;
/* We should never get an invalid register number here. */
if ((unsigned int) reg->value > 60)
{
- sprintf (buf, "invalid register number `%d'", reg->value);
+ /* xgettext:c-format */
+ sprintf (buf, _("invalid register number `%d'"), reg->value);
*errmsg = buf;
}
else
long value;
const char **errmsg;
{
- insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ long minval, maxval;
+ static char buf[100];
+
+ if (reg != NULL)
+ {
+ *errmsg = "register appears where shimm value expected";
+ }
+ else
+ {
+ /* This is *way* more general than necessary, but maybe some day it'll
+ be useful. */
+ if (operand->flags & ARC_OPERAND_SIGNED)
+ {
+ minval = -(1 << (operand->bits - 1));
+ maxval = (1 << (operand->bits - 1)) - 1;
+ }
+ else
+ {
+ minval = 0;
+ maxval = (1 << operand->bits) - 1;
+ }
+ if (value < minval || value > maxval)
+ {
+ /* xgettext:c-format */
+ sprintf (buf, _("value won't fit in range %ld - %ld"),
+ minval, maxval);
+ *errmsg = buf;
+ }
+ else
+ insn |= (value & ((1 << operand->bits) - 1)) << operand->shift;
+ }
return insn;
}
const char **errmsg;
{
if (limm_p)
- /* FIXME: put an abort here and see what happens. */
; /* nothing to do, gas does it */
return insn;
}
const char **errmsg;
{
if (value & 3)
- *errmsg = "branch address not on 4 byte boundary";
+ *errmsg = _("branch address not on 4 byte boundary");
insn |= ((value >> 2) & ((1 << operand->bits) - 1)) << operand->shift;
return insn;
}
const char **errmsg;
{
if (limm_p)
- /* FIXME: put an abort here and see what happens. */
; /* nothing to do */
return insn;
}
{
const struct arc_operand_value *reg = lookup_register (REG, regno);
- if (!reg)
+ if (reg == NULL)
abort ();
- if (opval)
+ if (opval != NULL)
*opval = reg;
value = regno;
}
/* This is really a constant, but tell the caller it has a special
name. */
- if (reg && opval)
+ if (reg != NULL && opval != NULL)
*opval = reg;
}
return 0;
val = arc_opcode_lookup_suffix (operand, 1);
- if (opval && val)
+ if (opval != NULL && val != NULL)
*opval = val;
return val->value;
}
/* Ignore NULL values of `val'. Several condition code values are
reserved for extensions. */
- if (opval && val)
+ if (opval != NULL && val != NULL)
*opval = val;
return cond;
}
const struct arc_operand_value **opval;
int *invalid;
{
- /* ??? This misses the case where B == ARC_REG_SHIMM_UPDATE &&
+ /* This misses the case where B == ARC_REG_SHIMM_UPDATE &&
C == ARC_REG_SHIMM (or vice versa). No big deal. Those insns will get
printed as "and"s. */
if (((insn[0] >> ARC_SHIFT_REGB) & ARC_MASK_REG)
!= ((insn[0] >> ARC_SHIFT_REGC) & ARC_MASK_REG))
- if (invalid)
+ if (invalid != NULL)
*invalid = 1;
return 0;
projects / deliverable / binutils-gdb.git / blobdiff