/* ARC Auxiliary register definitions
- Copyright (C) 2015-2016 Free Software Foundation, Inc.
+ Copyright (C) 2015-2020 Free Software Foundation, Inc.
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
along with this program; if not, write to the Free Software Foundation,
Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
-DEF (0x0, STATUS)
-DEF (0x1, SEMAPHORE)
-DEF (0x2, LP_START)
-DEF (0x3, LP_END)
-DEF (0x4, IDENTITY)
-DEF (0x5, DEBUG)
-DEF (0x6, PC)
-DEF (0x7, ADCR)
-DEF (0x8, APCR)
-DEF (0x9, ACR)
-DEF (0xA, STATUS32)
-DEF (0xB, STATUS32_L1)
-DEF (0xC, STATUS32_L2)
-DEF (0xF, BPU_FLUSH)
-DEF (0x10, IVIC)
-DEF (0x10, IC_IVIC)
-DEF (0x11, CHE_MODE)
-DEF (0x11, IC_CTRL)
-DEF (0x12, MULHI)
-DEF (0x13, LOCKLINE)
-DEF (0x13, IC_LIL)
-DEF (0x14, DMC_CODE_RAM)
-DEF (0x15, TAG_ADDR_MASK)
-DEF (0x16, TAG_DATA_MASK)
-DEF (0x17, LINE_LENGTH_MASK)
-DEF (0x18, AUX_LDST_RAM)
-DEF (0x18, AUX_DCCM)
-DEF (0x19, UNLOCKLINE)
-DEF (0x19, IC_IVIL)
-DEF (0x1A, IC_RAM_ADDRESS)
-DEF (0x1B, IC_TAG)
-DEF (0x1C, IC_WP)
-DEF (0x1D, IC_DATA)
-DEF (0x20, SRAM_SEQ)
-DEF (0x21, COUNT0)
-DEF (0x22, CONTROL0)
-DEF (0x23, LIMIT0)
-DEF (0x24, PCPORT)
-DEF (0x25, INT_VECTOR_BASE)
-DEF (0x26, AUX_VBFDW_MODE)
-DEF (0x26, JLI_BASE)
-DEF (0x27, AUX_VBFDW_BM0)
-DEF (0x28, AUX_VBFDW_BM1)
-DEF (0x29, AUX_VBFDW_ACCU)
-DEF (0x2A, AUX_VBFDW_OFST)
-DEF (0x2B, AUX_VBFDW_INTSTAT)
-DEF (0x2C, AUX_XMAC0_24)
-DEF (0x2D, AUX_XMAC1_24)
-DEF (0x2E, AUX_XMAC2_24)
-DEF (0x2F, AUX_FBF_STORE_16)
-DEF (0x30, AX0)
-DEF (0x31, AX1)
-DEF (0x32, AUX_CRC_POLY)
-DEF (0x33, AUX_CRC_MODE)
-DEF (0x34, MX0)
-DEF (0x35, MX1)
-DEF (0x36, MY0)
-DEF (0x37, MY1)
-DEF (0x38, XYCONFIG)
-DEF (0x39, SCRATCH_A)
-DEF (0x3A, BURSTSYS)
-DEF (0x3A, TSCH)
-DEF (0x3B, BURSTXYM)
-DEF (0x3C, BURSTSZ)
-DEF (0x3D, BURSTVAL)
-DEF (0x40, XTP_NEWVAL)
-DEF (0x41, AUX_MACMODE)
-DEF (0x42, LSP_NEWVAL)
-DEF (0x43, AUX_IRQ_LV12)
-DEF (0x44, AUX_XMAC0)
-DEF (0x45, AUX_XMAC1)
-DEF (0x46, AUX_XMAC2)
-DEF (0x47, DC_IVDC)
-DEF (0x48, DC_CTRL)
-DEF (0x49, DC_LDL)
-DEF (0x4A, DC_IVDL)
-DEF (0x4B, DC_FLSH)
-DEF (0x4C, DC_FLDL)
-DEF (0x50, HEXDATA)
-DEF (0x51, HEXCTRL)
-DEF (0x52, LED)
-DEF (0x56, DILSTAT)
-DEF (0x57, SWSTAT)
-DEF (0x58, DC_RAM_ADDR)
-DEF (0x59, DC_TAG)
-DEF (0x5A, DC_WP)
-DEF (0x5B, DC_DATA)
-DEF (0x61, DCCM_BASE_BUILD)
-DEF (0x62, CRC_BUILD)
-DEF (0x63, BTA_LINK_BUILD)
-DEF (0x64, VBFDW_BUILD)
-DEF (0x65, EA_BUILD)
-DEF (0x66, DATASPACE)
-DEF (0x67, MEMSUBSYS)
-DEF (0x68, VECBASE_AC_BUILD)
-DEF (0x69, P_BASE_ADDR)
-DEF (0x6A, DATA_UNCACHED_BUILD)
-DEF (0x6B, FP_BUILD)
-DEF (0x6C, DPFP_BUILD)
-DEF (0x6D, MPU_BUILD)
-DEF (0x6E, RF_BUILD)
-DEF (0x6F, MMU_BUILD)
-DEF (0x70, AA2_BUILD)
-DEF (0x71, VECBASE_BUILD)
-DEF (0x72, D_CACHE_BUILD)
-DEF (0x73, MADI_BUILD)
-DEF (0x74, DCCM_BUILD)
-DEF (0x75, TIMER_BUILD)
-DEF (0x76, AP_BUILD)
-DEF (0x77, I_CACHE_BUILD)
-DEF (0x78, ICCM_BUILD)
-DEF (0x79, DSPRAM_BUILD)
-DEF (0x7A, MAC_BUILD)
-DEF (0x7B, MULTIPLY_BUILD)
-DEF (0x7C, SWAP_BUILD)
-DEF (0x7D, NORM_BUILD)
-DEF (0x7E, MINMAX_BUILD)
-DEF (0x7F, BARREL_BUILD)
-DEF (0x80, AX0)
-DEF (0x81, AX1)
-DEF (0x82, AX2)
-DEF (0x83, AX3)
-DEF (0x84, AY0)
-DEF (0x85, AY1)
-DEF (0x86, AY2)
-DEF (0x87, AY3)
-DEF (0x88, MX00)
-DEF (0x89, MX01)
-DEF (0x8A, MX10)
-DEF (0x8B, MX11)
-DEF (0x8C, MX20)
-DEF (0x8D, MX21)
-DEF (0x8E, MX30)
-DEF (0x8F, MX31)
-DEF (0x90, MY00)
-DEF (0x91, MY01)
-DEF (0x92, MY10)
-DEF (0x93, MY11)
-DEF (0x94, MY20)
-DEF (0x95, MY21)
-DEF (0x96, MY30)
-DEF (0x97, MY31)
-DEF (0x98, XYCONFIG)
-DEF (0x99, BURSTSYS)
-DEF (0x9A, BURSTXYM)
-DEF (0x9B, BURSTSZ)
-DEF (0x9C, BURSTVAL)
-DEF (0x9D, XYLSBASEX)
-DEF (0x9E, XYLSBASEY)
-DEF (0x9F, AUX_XMACLW_H)
-DEF (0xA0, AUX_XMACLW_L)
-DEF (0xA1, SE_CTRL)
-DEF (0xA2, SE_STAT)
-DEF (0xA3, SE_ERR)
-DEF (0xA4, SE_EADR)
-DEF (0xA5, SE_SPC)
-DEF (0xA6, SDM_BASE)
-DEF (0xA7, SCM_BASE)
-DEF (0xA8, SE_DBG_CTRL)
-DEF (0xA9, SE_DBG_DATA0)
-DEF (0xAA, SE_DBG_DATA1)
-DEF (0xAB, SE_DBG_DATA2)
-DEF (0xAC, SE_DBG_DATA3)
-DEF (0xAD, SE_WATCH)
-DEF (0xC0, BPU_BUILD)
-DEF (0xC1, ARC600_BUILD_CONFIG)
-DEF (0xC2, ISA_CONFIG)
-DEF (0xF4, HWP_BUILD)
-DEF (0xF5, PCT_BUILD)
-DEF (0xF6, CC_BUILD)
-DEF (0xF7, PM_BCR)
-DEF (0xF8, SCQ_SWITCH_BUILD)
-DEF (0xF9, VRAPTOR_BUILD)
-DEF (0xFA, DMA_CONFIG)
-DEF (0xFB, SIMD_CONFIG)
-DEF (0xFC, VLC_BUILD)
-DEF (0xFD, SIMD_DMA_BUILD)
-DEF (0xFE, IFETCH_QUEUE_BUILD)
-DEF (0xFF, SMART_BUILD)
-DEF (0x100, COUNT1)
-DEF (0x101, CONTROL1)
-DEF (0x102, LIMIT1)
-DEF (0x103, TIMER_XX)
-DEF (0x120, ARCANGEL_PERIPH_XX)
-DEF (0x140, PERIPH_XX)
-DEF (0x200, AUX_IRQ_LEV)
-DEF (0x201, AUX_IRQ_HINT)
-DEF (0x202, AUX_INTER_CORE_INTERRUPT)
-DEF (0x210, AES_AUX_0)
-DEF (0x211, AES_AUX_1)
-DEF (0x212, AES_AUX_2)
-DEF (0x213, AES_CRYPT_MODE)
-DEF (0x214, AES_AUXS)
-DEF (0x215, AES_AUXI)
-DEF (0x216, AES_AUX_3)
-DEF (0x217, AES_AUX_4)
-DEF (0x218, ARITH_CTL_AUX)
-DEF (0x219, DES_AUX)
-DEF (0x220, AP_AMV0)
-DEF (0x221, AP_AMM0)
-DEF (0x222, AP_AC0)
-DEF (0x223, AP_AMV1)
-DEF (0x224, AP_AMM1)
-DEF (0x225, AP_AC1)
-DEF (0x226, AP_AMV2)
-DEF (0x227, AP_AMM2)
-DEF (0x228, AP_AC2)
-DEF (0x229, AP_AMV3)
-DEF (0x22A, AP_AMM3)
-DEF (0x22B, AP_AC3)
-DEF (0x22C, AP_AMV4)
-DEF (0x22D, AP_AMM4)
-DEF (0x22E, AP_AC4)
-DEF (0x22F, AP_AMV5)
-DEF (0x230, AP_AMM5)
-DEF (0x231, AP_AC5)
-DEF (0x232, AP_AMV6)
-DEF (0x233, AP_AMM6)
-DEF (0x234, AP_AC6)
-DEF (0x235, AP_AMV7)
-DEF (0x236, AP_AMM7)
-DEF (0x237, AP_AC7)
-DEF (0x278, PCT_CONTROL)
-DEF (0x279, PCT_BANK)
-DEF (0x300, FP_STATUS)
-DEF (0x301, AUX_DPFP1L)
-DEF (0x301, D1L)
-DEF (0x302, AUX_DPFP1H)
-DEF (0x302, D1H)
-DEF (0x303, AUX_DPFP2L)
-DEF (0x303, D2L)
-DEF (0x304, AUX_DPFP2H)
-DEF (0x304, D2H)
-DEF (0x305, DPFP_STATUS)
-DEF (0x306, RTT)
-DEF (0x400, ERET)
-DEF (0x401, ERBTA)
-DEF (0x402, ERSTATUS)
-DEF (0x403, ECR)
-DEF (0x404, EFA)
-DEF (0x405, TLBPD0)
-DEF (0x406, TLBPD1)
-DEF (0x407, TLBIndex)
-DEF (0x408, TLBCommand)
-DEF (0x409, PID)
-DEF (0x409, MPUEN)
-DEF (0x40A, ICAUSE1)
-DEF (0x40B, ICAUSE2)
-DEF (0x40C, AUX_IENABLE)
-DEF (0x40D, AUX_ITRIGGER)
-DEF (0x410, XPU)
-DEF (0x412, BTA)
-DEF (0x413, BTA_L1)
-DEF (0x414, BTA_L2)
-DEF (0x415, AUX_IRQ_PULSE_CANCEL)
-DEF (0x416, AUX_IRQ_PENDING)
-DEF (0x418, SCRATCH_DATA0)
-DEF (0x420, MPUIC)
-DEF (0x421, MPUFA)
-DEF (0x422, MPURDB0)
-DEF (0x423, MPURDP0)
-DEF (0x424, MPURDB1)
-DEF (0x425, MPURDP1)
-DEF (0x426, MPURDB2)
-DEF (0x427, MPURDP2)
-DEF (0x428, MPURDB3)
-DEF (0x429, MPURDP3)
-DEF (0x42A, MPURDB4)
-DEF (0x42B, MPURDP4)
-DEF (0x42C, MPURDB5)
-DEF (0x42D, MPURDP5)
-DEF (0x42E, MPURDB6)
-DEF (0x42F, MPURDP6)
-DEF (0x430, MPURDB7)
-DEF (0x431, MPURDP7)
-DEF (0x432, MPURDB8)
-DEF (0x433, MPURDP8)
-DEF (0x434, MPURDB9)
-DEF (0x435, MPURDP9)
-DEF (0x436, MPURDB10)
-DEF (0x437, MPURDP10)
-DEF (0x438, MPURDB11)
-DEF (0x439, MPURDP11)
-DEF (0x43A, MPURDB12)
-DEF (0x43B, MPURDP12)
-DEF (0x43C, MPURDB13)
-DEF (0x43D, MPURDP13)
-DEF (0x43E, MPURDB14)
-DEF (0x43F, MPURDP14)
-DEF (0x440, MPURDB15)
-DEF (0x441, MPURDP15)
-DEF (0x44F, EIA_FLAGS)
-DEF (0x450, PM_STATUS)
-DEF (0x451, WAKE)
-DEF (0x452, DVFS_PERFORMANCE)
-DEF (0x453, PWR_CTRL)
-DEF (0x500, AUX_VLC_BUF_IDX)
-DEF (0x501, AUX_VLC_READ_BUF)
-DEF (0x502, AUX_VLC_VALID_BITS)
-DEF (0x503, AUX_VLC_BUF_IN)
-DEF (0x504, AUX_VLC_BUF_FREE)
-DEF (0x505, AUX_VLC_IBUF_STATUS)
-DEF (0x506, AUX_VLC_SETUP)
-DEF (0x507, AUX_VLC_BITS)
-DEF (0x508, AUX_VLC_TABLE)
-DEF (0x509, AUX_VLC_GET_SYMBOL)
-DEF (0x50A, AUX_VLC_READ_SYMBOL)
-DEF (0x510, AUX_UCAVLC_SETUP)
-DEF (0x511, AUX_UCAVLC_STATE)
-DEF (0x512, AUX_CAVLC_ZERO_LEFT)
-DEF (0x514, AUX_UVLC_I_STATE)
-DEF (0x51C, AUX_VLC_DMA_PTR)
-DEF (0x51D, AUX_VLC_DMA_END)
-DEF (0x51E, AUX_VLC_DMA_ESC)
-DEF (0x51F, AUX_VLC_DMA_CTRL)
-DEF (0x520, AUX_VLC_GET_0BIT)
-DEF (0x521, AUX_VLC_GET_1BIT)
-DEF (0x522, AUX_VLC_GET_2BIT)
-DEF (0x523, AUX_VLC_GET_3BIT)
-DEF (0x524, AUX_VLC_GET_4BIT)
-DEF (0x525, AUX_VLC_GET_5BIT)
-DEF (0x526, AUX_VLC_GET_6BIT)
-DEF (0x527, AUX_VLC_GET_7BIT)
-DEF (0x528, AUX_VLC_GET_8BIT)
-DEF (0x529, AUX_VLC_GET_9BIT)
-DEF (0x52A, AUX_VLC_GET_10BIT)
-DEF (0x52B, AUX_VLC_GET_11BIT)
-DEF (0x52C, AUX_VLC_GET_12BIT)
-DEF (0x52D, AUX_VLC_GET_13BIT)
-DEF (0x52E, AUX_VLC_GET_14BIT)
-DEF (0x52F, AUX_VLC_GET_15BIT)
-DEF (0x530, AUX_VLC_GET_16BIT)
-DEF (0x531, AUX_VLC_GET_17BIT)
-DEF (0x532, AUX_VLC_GET_18BIT)
-DEF (0x533, AUX_VLC_GET_19BIT)
-DEF (0x534, AUX_VLC_GET_20BIT)
-DEF (0x535, AUX_VLC_GET_21BIT)
-DEF (0x536, AUX_VLC_GET_22BIT)
-DEF (0x537, AUX_VLC_GET_23BIT)
-DEF (0x538, AUX_VLC_GET_24BIT)
-DEF (0x539, AUX_VLC_GET_25BIT)
-DEF (0x53A, AUX_VLC_GET_26BIT)
-DEF (0x53B, AUX_VLC_GET_27BIT)
-DEF (0x53C, AUX_VLC_GET_28BIT)
-DEF (0x53D, AUX_VLC_GET_29BIT)
-DEF (0x53E, AUX_VLC_GET_30BIT)
-DEF (0x53F, AUX_VLC_GET_31BIT)
-DEF (0x540, AUX_CABAC_CTRL)
-DEF (0x541, AUX_CABAC_CTX_STATE)
-DEF (0x542, AUX_CABAC_COD_PARAM)
-DEF (0x543, AUX_CABAC_MISC0)
-DEF (0x544, AUX_CABAC_MISC1)
-DEF (0x545, AUX_CABAC_MISC2)
-DEF (0x600, ARC600_BUILD_CONFIG)
-DEF (0x700, SMART_CONTROL)
-DEF (0x701, SMART_DATA_0)
-DEF (0x701, SMART_DATA_1)
-DEF (0x701, SMART_DATA_2)
-DEF (0x701, SMART_DATA_3)
+DEF (0x0, ARC_OPCODE_ARCV1, NONE, status)
+DEF (0x1, ARC_OPCODE_ARCV1, NONE, semaphore)
+DEF (0x2, ARC_OPCODE_ARCALL, NONE, lp_start)
+DEF (0x3, ARC_OPCODE_ARCALL, NONE, lp_end)
+DEF (0x4, ARC_OPCODE_ARCALL, NONE, identity)
+DEF (0x5, ARC_OPCODE_ARCALL, NONE, debug)
+DEF (0x6, ARC_OPCODE_ARCALL, NONE, pc)
+DEF (0x7, ARC_OPCODE_ARCv2HS, NONE, memseg)
+DEF (0x7, ARC_OPCODE_ARCV1, NONE, adcr)
+DEF (0x8, ARC_OPCODE_ARCV1, NONE, apcr)
+DEF (0x9, ARC_OPCODE_ARCV1, NONE, acr)
+DEF (0x9, ARC_OPCODE_ARCv2EM, NONE, sec_stat)
+DEF (0xa, ARC_OPCODE_ARCALL, NONE, status32)
+DEF (0xb, ARC_OPCODE_ARCV1, NONE, status32_l1)
+DEF (0xb, ARC_OPCODE_ARCV2, NONE, status32_p0)
+DEF (0xc, ARC_OPCODE_ARCV1, NONE, status32_l2)
+DEF (0xc, ARC_OPCODE_ARCv2EM, NONE, sec_extra)
+DEF (0xd, ARC_OPCODE_ARCV2, NONE, aux_user_sp)
+DEF (0xe, ARC_OPCODE_ARCV2, NONE, aux_irq_ctrl)
+DEF (0xe, ARC_OPCODE_ARC700, NONE, clk_enable)
+DEF (0xf, ARC_OPCODE_ARC700, NONE, bpu_flush)
+DEF (0xf, ARC_OPCODE_ARCv2HS, NONE, debugi)
+DEF (0x10, ARC_OPCODE_ARCV1, NONE, ivic)
+DEF (0x10, ARC_OPCODE_ARCALL, NONE, ic_ivic)
+DEF (0x11, ARC_OPCODE_ARCV1, NONE, che_mode)
+DEF (0x11, ARC_OPCODE_ARCALL, NONE, ic_ctrl)
+DEF (0x12, ARC_OPCODE_ARC600, NONE, mulhi)
+DEF (0x12, ARC_OPCODE_ARCv2HS, NONE, ic_startr_ext)
+DEF (0x13, ARC_OPCODE_ARCV1, NONE, lockline)
+DEF (0x13, ARC_OPCODE_ARCV2, NONE, ic_lil)
+DEF (0x14, ARC_OPCODE_ARC600, NONE, dmc_code_ram)
+DEF (0x15, ARC_OPCODE_ARCV1, NONE, tag_addr_mask)
+DEF (0x16, ARC_OPCODE_ARCV1, NONE, tag_data_mask)
+DEF (0x16, ARC_OPCODE_ARCv2HS, NONE, ic_ivir)
+DEF (0x17, ARC_OPCODE_ARCV1, NONE, line_length_mask)
+DEF (0x17, ARC_OPCODE_ARCv2HS, NONE, ic_endr)
+DEF (0x18, ARC_OPCODE_ARC600, NONE, aux_ldst_ram)
+DEF (0x18, ARC_OPCODE_NONE, NONE, aux_dccm)
+DEF (0x19, ARC_OPCODE_ARCV1, NONE, unlockline)
+DEF (0x19, ARC_OPCODE_ARCALL, NONE, ic_ivil)
+DEF (0x1a, ARC_OPCODE_ARCALL, NONE, ic_ram_address)
+DEF (0x1b, ARC_OPCODE_ARCALL, NONE, ic_tag)
+DEF (0x1c, ARC_OPCODE_ARCALL, NONE, ic_wp)
+DEF (0x1d, ARC_OPCODE_ARCALL, NONE, ic_data)
+DEF (0x1e, ARC_OPCODE_ARCALL, NONE, ic_ptag)
+DEF (0x1f, ARC_OPCODE_ARCv2EM, NONE, debugi)
+DEF (0x1f, ARC_OPCODE_ARCv2HS, NONE, ic_endr_ext)
+DEF (0x20, ARC_OPCODE_ARC600, NONE, sram_seq)
+DEF (0x21, ARC_OPCODE_ARCALL, NONE, count0)
+DEF (0x22, ARC_OPCODE_ARCALL, NONE, control0)
+DEF (0x23, ARC_OPCODE_ARCALL, NONE, limit0)
+DEF (0x24, ARC_OPCODE_ARCV1, NONE, pcport)
+DEF (0x25, ARC_OPCODE_ARC700, NONE, int_vector_base)
+DEF (0x25, ARC_OPCODE_ARCV2, NONE, int_vector_base)
+DEF (0x26, ARC_OPCODE_ARC600, NONE, aux_vbfdw_mode)
+DEF (0x27, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm0)
+DEF (0x28, ARC_OPCODE_ARC600, NONE, aux_vbfdw_bm1)
+DEF (0x29, ARC_OPCODE_ARC600, NONE, aux_vbfdw_accu)
+DEF (0x2a, ARC_OPCODE_ARC600, NONE, aux_vbfdw_ofst)
+DEF (0x2b, ARC_OPCODE_ARC600, NONE, aux_vbfdw_intstat)
+DEF (0x2c, ARC_OPCODE_ARC600, NONE, aux_xmac0_24)
+DEF (0x2d, ARC_OPCODE_ARC600, NONE, aux_xmac1_24)
+DEF (0x2e, ARC_OPCODE_ARC600, NONE, aux_xmac2_24)
+DEF (0x2f, ARC_OPCODE_ARC600, NONE, aux_fbf_store_16)
+DEF (0x30, ARC_OPCODE_ARCv2EM, NONE, acg_ctrl)
+DEF (0x30, ARC_OPCODE_NONE, NONE, ax0)
+DEF (0x31, ARC_OPCODE_NONE, NONE, ax1)
+DEF (0x32, ARC_OPCODE_NONE, NONE, aux_crc_poly)
+DEF (0x33, ARC_OPCODE_NONE, NONE, aux_crc_mode)
+DEF (0x34, ARC_OPCODE_NONE, NONE, mx0)
+DEF (0x35, ARC_OPCODE_NONE, NONE, mx1)
+DEF (0x36, ARC_OPCODE_NONE, NONE, my0)
+DEF (0x37, ARC_OPCODE_NONE, NONE, my1)
+DEF (0x38, ARC_OPCODE_NONE, NONE, xyconfig)
+DEF (0x38, ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp)
+DEF (0x39, ARC_OPCODE_NONE, NONE, scratch_a)
+DEF (0x39, ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp)
+DEF (0x3a, ARC_OPCODE_NONE, NONE, burstsys)
+DEF (0x3a, ARC_OPCODE_NONE, NONE, tsch)
+DEF (0x3a, ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp)
+DEF (0x3b, ARC_OPCODE_NONE, NONE, burstxym)
+DEF (0x3c, ARC_OPCODE_NONE, NONE, burstsz)
+DEF (0x3d, ARC_OPCODE_NONE, NONE, burstval)
+DEF (0x3e, ARC_OPCODE_ARCv2EM, NONE, aux_sec_ctrl)
+DEF (0x3f, ARC_OPCODE_ARCv2EM, NONE, erp_control)
+DEF (0x40, ARC_OPCODE_ARCv2EM, NONE, rferp_status0)
+DEF (0x41, ARC_OPCODE_ARCv2EM, NONE, rferp_status1)
+DEF (0x40, ARC_OPCODE_ARC600, NONE, xtp_newval)
+DEF (0x41, ARC_OPCODE_ARCV1, NONE, aux_macmode)
+DEF (0x42, ARC_OPCODE_ARC600, NONE, lsp_newval)
+DEF (0x43, ARC_OPCODE_ARCV1, NONE, aux_irq_lv12)
+DEF (0x43, ARC_OPCODE_ARCV2, NONE, aux_irq_act)
+DEF (0x44, ARC_OPCODE_ARCV1, NONE, aux_xmac0)
+DEF (0x45, ARC_OPCODE_ARCV1, NONE, aux_xmac1)
+DEF (0x46, ARC_OPCODE_ARCV1, NONE, aux_xmac2)
+DEF (0x47, ARC_OPCODE_ARCALL, NONE, dc_ivdc)
+DEF (0x48, ARC_OPCODE_ARCALL, NONE, dc_ctrl)
+DEF (0x49, ARC_OPCODE_ARCALL, NONE, dc_ldl)
+DEF (0x4a, ARC_OPCODE_ARCALL, NONE, dc_ivdl)
+DEF (0x4b, ARC_OPCODE_ARCALL, NONE, dc_flsh)
+DEF (0x4c, ARC_OPCODE_ARCALL, NONE, dc_fldl)
+DEF (0x50, ARC_OPCODE_NONE, NONE, hexdata)
+DEF (0x51, ARC_OPCODE_NONE, NONE, hexctrl)
+DEF (0x52, ARC_OPCODE_NONE, NONE, led)
+DEF (0x56, ARC_OPCODE_NONE, NONE, dilstat)
+DEF (0x57, ARC_OPCODE_ARC600, NONE, swstat)
+DEF (0x58, ARC_OPCODE_ARCALL, NONE, dc_ram_addr)
+DEF (0x59, ARC_OPCODE_ARCALL, NONE, dc_tag)
+DEF (0x5a, ARC_OPCODE_ARCALL, NONE, dc_wp)
+DEF (0x5b, ARC_OPCODE_ARCALL, NONE, dc_data)
+DEF (0x61, ARC_OPCODE_ARCALL, NONE, dccm_base_build)
+DEF (0x62, ARC_OPCODE_ARCALL, NONE, crc_build)
+DEF (0x63, ARC_OPCODE_ARCALL, NONE, bta_link_build)
+DEF (0x64, ARC_OPCODE_ARCALL, NONE, vbfdw_build)
+DEF (0x65, ARC_OPCODE_ARCALL, NONE, ea_build)
+DEF (0x66, ARC_OPCODE_ARCALL, NONE, dataspace)
+DEF (0x67, ARC_OPCODE_ARCALL, NONE, memsubsys)
+DEF (0x68, ARC_OPCODE_ARCALL, NONE, vecbase_ac_build)
+DEF (0x69, ARC_OPCODE_ARCALL, NONE, p_base_addr)
+DEF (0x6a, ARC_OPCODE_ARCALL, NONE, data_uncached_build)
+DEF (0x6b, ARC_OPCODE_ARCALL, NONE, fp_build)
+DEF (0x6c, ARC_OPCODE_ARCALL, NONE, dpfp_build)
+DEF (0x6d, ARC_OPCODE_ARCALL, NONE, mpu_build)
+DEF (0x6e, ARC_OPCODE_ARCALL, NONE, rf_build)
+DEF (0x6f, ARC_OPCODE_ARCALL, NONE, mmu_build)
+DEF (0x70, ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build)
+DEF (0x71, ARC_OPCODE_ARCALL, NONE, vecbase_build)
+DEF (0x72, ARC_OPCODE_ARCALL, NONE, d_cache_build)
+DEF (0x73, ARC_OPCODE_ARCALL, NONE, madi_build)
+DEF (0x74, ARC_OPCODE_ARCALL, NONE, dccm_build)
+DEF (0x75, ARC_OPCODE_ARCALL, NONE, timer_build)
+DEF (0x76, ARC_OPCODE_ARCALL, NONE, ap_build)
+DEF (0x77, ARC_OPCODE_ARCALL, NONE, i_cache_build)
+DEF (0x78, ARC_OPCODE_ARCALL, NONE, iccm_build)
+DEF (0x79, ARC_OPCODE_ARCALL, NONE, dspram_build)
+DEF (0x7a, ARC_OPCODE_ARCALL, NONE, mac_build)
+DEF (0x7b, ARC_OPCODE_ARCALL, NONE, multiply_build)
+DEF (0x7c, ARC_OPCODE_ARCALL, NONE, swap_build)
+DEF (0x7d, ARC_OPCODE_ARCALL, NONE, norm_build)
+DEF (0x7e, ARC_OPCODE_ARCALL, NONE, minmax_build)
+DEF (0x7f, ARC_OPCODE_ARCALL, NONE, barrel_build)
+DEF (0x80, ARC_OPCODE_ARCALL, NONE, ax0)
+DEF (0x81, ARC_OPCODE_ARCALL, NONE, ax1)
+DEF (0x82, ARC_OPCODE_ARCALL, NONE, ax2)
+DEF (0x83, ARC_OPCODE_ARCALL, NONE, ax3)
+DEF (0x84, ARC_OPCODE_ARCALL, NONE, ay0)
+DEF (0x85, ARC_OPCODE_ARCALL, NONE, ay1)
+DEF (0x86, ARC_OPCODE_ARCALL, NONE, ay2)
+DEF (0x87, ARC_OPCODE_ARCALL, NONE, ay3)
+DEF (0x88, ARC_OPCODE_ARCALL, NONE, mx00)
+DEF (0x89, ARC_OPCODE_ARCALL, NONE, mx01)
+DEF (0x8a, ARC_OPCODE_ARCALL, NONE, mx10)
+DEF (0x8b, ARC_OPCODE_ARCALL, NONE, mx11)
+DEF (0x8c, ARC_OPCODE_ARCALL, NONE, mx20)
+DEF (0x8d, ARC_OPCODE_ARCALL, NONE, mx21)
+DEF (0x8e, ARC_OPCODE_ARCALL, NONE, mx30)
+DEF (0x8f, ARC_OPCODE_ARCALL, NONE, mx31)
+DEF (0x90, ARC_OPCODE_ARCALL, NONE, my00)
+DEF (0x91, ARC_OPCODE_ARCALL, NONE, my01)
+DEF (0x92, ARC_OPCODE_ARCALL, NONE, my10)
+DEF (0x93, ARC_OPCODE_ARCALL, NONE, my11)
+DEF (0x94, ARC_OPCODE_ARCALL, NONE, my20)
+DEF (0x95, ARC_OPCODE_ARCALL, NONE, my21)
+DEF (0x96, ARC_OPCODE_ARCALL, NONE, my30)
+DEF (0x97, ARC_OPCODE_ARCALL, NONE, my31)
+DEF (0x98, ARC_OPCODE_ARCALL, NONE, xyconfig)
+DEF (0x99, ARC_OPCODE_ARCALL, NONE, burstsys)
+DEF (0x9a, ARC_OPCODE_ARCALL, NONE, burstxym)
+DEF (0x9b, ARC_OPCODE_ARCALL, NONE, burstsz)
+DEF (0x9c, ARC_OPCODE_ARCALL, NONE, burstval)
+DEF (0x9d, ARC_OPCODE_ARCALL, NONE, xylsbasex)
+DEF (0x9e, ARC_OPCODE_ARCALL, NONE, xylsbasey)
+DEF (0x9f, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_h)
+DEF (0xa0, ARC_OPCODE_ARCALL, NONE, aux_xmaclw_l)
+DEF (0xa1, ARC_OPCODE_ARCALL, NONE, se_ctrl)
+DEF (0xa2, ARC_OPCODE_ARCALL, NONE, se_stat)
+DEF (0xa3, ARC_OPCODE_ARCALL, NONE, se_err)
+DEF (0xa4, ARC_OPCODE_ARCALL, NONE, se_eadr)
+DEF (0xa5, ARC_OPCODE_ARCALL, NONE, se_spc)
+DEF (0xa6, ARC_OPCODE_ARCALL, NONE, sdm_base)
+DEF (0xa7, ARC_OPCODE_ARCALL, NONE, scm_base)
+DEF (0xa8, ARC_OPCODE_ARCALL, NONE, se_dbg_ctrl)
+DEF (0xa9, ARC_OPCODE_ARCALL, NONE, se_dbg_data0)
+DEF (0xaa, ARC_OPCODE_ARCALL, NONE, se_dbg_data1)
+DEF (0xab, ARC_OPCODE_ARCALL, NONE, se_dbg_data2)
+DEF (0xac, ARC_OPCODE_ARCALL, NONE, se_dbg_data3)
+DEF (0xad, ARC_OPCODE_ARCALL, NONE, se_watch)
+DEF (0xc0, ARC_OPCODE_ARCALL, NONE, bpu_build)
+DEF (0xc1, ARC_OPCODE_ARC600, NONE, arc600_build_config)
+DEF (0xc2, ARC_OPCODE_ARCALL, NONE, isa_config)
+DEF (0xf4, ARC_OPCODE_ARCALL, NONE, hwp_build)
+DEF (0xf5, ARC_OPCODE_ARCALL, NONE, pct_build)
+DEF (0xf6, ARC_OPCODE_ARCALL, NONE, cc_build)
+DEF (0xf7, ARC_OPCODE_ARCALL, NONE, pm_bcr)
+DEF (0xf8, ARC_OPCODE_ARCALL, NONE, scq_switch_build)
+DEF (0xf9, ARC_OPCODE_ARCALL, NONE, vraptor_build)
+DEF (0xfa, ARC_OPCODE_ARCALL, NONE, dma_config)
+DEF (0xfb, ARC_OPCODE_ARCALL, NONE, simd_config)
+DEF (0xfc, ARC_OPCODE_ARCALL, NONE, vlc_build)
+DEF (0xfd, ARC_OPCODE_ARCALL, NONE, simd_dma_build)
+DEF (0xfe, ARC_OPCODE_ARCALL, NONE, ifetch_queue_build)
+DEF (0xff, ARC_OPCODE_ARCALL, NONE, smart_build)
+DEF (0x100, ARC_OPCODE_ARCALL, NONE, count1)
+DEF (0x101, ARC_OPCODE_ARCALL, NONE, control1)
+DEF (0x102, ARC_OPCODE_ARCALL, NONE, limit1)
+DEF (0x103, ARC_OPCODE_ARCALL, NONE, timer_xx)
+DEF (0x200, ARC_OPCODE_ARCV1, NONE, aux_irq_lev)
+DEF (0x200, ARC_OPCODE_ARCV2, NONE, irq_priority_pending)
+DEF (0x201, ARC_OPCODE_ARCALL, NONE, aux_irq_hint)
+DEF (0x202, ARC_OPCODE_ARC600, NONE, aux_inter_core_interrupt)
+DEF (0x206, ARC_OPCODE_ARCV2, NONE, irq_priority)
+DEF (0x210, ARC_OPCODE_ARC700, NONE, aes_aux_0)
+DEF (0x211, ARC_OPCODE_ARC700, NONE, aes_aux_1)
+DEF (0x212, ARC_OPCODE_ARC700, NONE, aes_aux_2)
+DEF (0x213, ARC_OPCODE_ARC700, NONE, aes_crypt_mode)
+DEF (0x214, ARC_OPCODE_ARC700, NONE, aes_auxs)
+DEF (0x215, ARC_OPCODE_ARC700, NONE, aes_auxi)
+DEF (0x216, ARC_OPCODE_ARC700, NONE, aes_aux_3)
+DEF (0x217, ARC_OPCODE_ARC700, NONE, aes_aux_4)
+DEF (0x218, ARC_OPCODE_ARC700, NONE, arith_ctl_aux)
+DEF (0x219, ARC_OPCODE_ARC700, NONE, des_aux)
+DEF (0x220, ARC_OPCODE_ARCALL, NONE, ap_amv0)
+DEF (0x221, ARC_OPCODE_ARCALL, NONE, ap_amm0)
+DEF (0x222, ARC_OPCODE_ARCALL, NONE, ap_ac0)
+DEF (0x223, ARC_OPCODE_ARCALL, NONE, ap_amv1)
+DEF (0x224, ARC_OPCODE_ARCALL, NONE, ap_amm1)
+DEF (0x225, ARC_OPCODE_ARCALL, NONE, ap_ac1)
+DEF (0x226, ARC_OPCODE_ARCALL, NONE, ap_amv2)
+DEF (0x227, ARC_OPCODE_ARCALL, NONE, ap_amm2)
+DEF (0x228, ARC_OPCODE_ARCALL, NONE, ap_ac2)
+DEF (0x229, ARC_OPCODE_ARCALL, NONE, ap_amv3)
+DEF (0x22a, ARC_OPCODE_ARCALL, NONE, ap_amm3)
+DEF (0x22b, ARC_OPCODE_ARCALL, NONE, ap_ac3)
+DEF (0x22c, ARC_OPCODE_ARCALL, NONE, ap_amv4)
+DEF (0x22d, ARC_OPCODE_ARCALL, NONE, ap_amm4)
+DEF (0x22e, ARC_OPCODE_ARCALL, NONE, ap_ac4)
+DEF (0x22f, ARC_OPCODE_ARCALL, NONE, ap_amv5)
+DEF (0x230, ARC_OPCODE_ARCALL, NONE, ap_amm5)
+DEF (0x231, ARC_OPCODE_ARCALL, NONE, ap_ac5)
+DEF (0x232, ARC_OPCODE_ARCALL, NONE, ap_amv6)
+DEF (0x233, ARC_OPCODE_ARCALL, NONE, ap_amm6)
+DEF (0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6)
+DEF (0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7)
+DEF (0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7)
+DEF (0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7)
+DEF (0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top)
+DEF (0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base)
+DEF (0x290, ARC_OPCODE_ARCV2, NONE, jli_base)
+DEF (0x291, ARC_OPCODE_ARCV2, NONE, ldi_base)
+DEF (0x292, ARC_OPCODE_ARCV2, NONE, ei_base)
+DEF (0x300, ARC_OPCODE_ARCFPX, DPX, fp_status)
+DEF (0x301, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1l)
+DEF (0x301, ARC_OPCODE_ARCFPX, DPX, d1l)
+DEF (0x302, ARC_OPCODE_ARCFPX, DPX, aux_dpfp1h)
+DEF (0x302, ARC_OPCODE_ARCFPX, DPX, d1h)
+DEF (0x302, ARC_OPCODE_ARCv2EM, DPA, d1l)
+DEF (0x303, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2l)
+DEF (0x303, ARC_OPCODE_ARCFPX, DPX, d2l)
+DEF (0x303, ARC_OPCODE_ARCv2EM, DPA, d1h)
+DEF (0x304, ARC_OPCODE_ARCFPX, DPX, aux_dpfp2h)
+DEF (0x304, ARC_OPCODE_ARCFPX, DPX, d2h)
+DEF (0x304, ARC_OPCODE_ARCv2EM, DPA, d2l)
+DEF (0x305, ARC_OPCODE_ARCFPX, DPX, dpfp_status)
+DEF (0x305, ARC_OPCODE_ARCv2EM, DPA, d2h)
+DEF (0x400, ARC_OPCODE_ARCALL, NONE, eret)
+DEF (0x401, ARC_OPCODE_ARCALL, NONE, erbta)
+DEF (0x402, ARC_OPCODE_ARCALL, NONE, erstatus)
+DEF (0x403, ARC_OPCODE_ARCALL, NONE, ecr)
+DEF (0x404, ARC_OPCODE_ARCALL, NONE, efa)
+DEF (0x405, ARC_OPCODE_ARC700, NONE, tlbpd0)
+DEF (0x406, ARC_OPCODE_ARC700, NONE, tlbpd1)
+DEF (0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat)
+DEF (0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except)
+DEF (0x407, ARC_OPCODE_ARC700, NONE, tlbindex)
+DEF (0x408, ARC_OPCODE_ARC700, NONE, tlbcommand)
+DEF (0x409, ARC_OPCODE_ARC700, NONE, pid)
+DEF (0x409, ARC_OPCODE_ARCALL, NONE, mpuen)
+DEF (0x40a, ARC_OPCODE_ARCALL, NONE, icause1)
+DEF (0x40b, ARC_OPCODE_ARCALL, NONE, icause2)
+DEF (0x40c, ARC_OPCODE_ARCALL, NONE, aux_ienable)
+DEF (0x40d, ARC_OPCODE_ARCALL, NONE, aux_itrigger)
+DEF (0x410, ARC_OPCODE_ARCALL, NONE, xpu)
+DEF (0x412, ARC_OPCODE_ARCALL, NONE, bta)
+DEF (0x413, ARC_OPCODE_ARC700, NONE, bta_l1)
+DEF (0x414, ARC_OPCODE_ARC700, NONE, bta_l2)
+DEF (0x415, ARC_OPCODE_ARCALL, NONE, aux_irq_pulse_cancel)
+DEF (0x416, ARC_OPCODE_ARCALL, NONE, aux_irq_pending)
+DEF (0x418, ARC_OPCODE_ARC700, NONE, scratch_data0)
+DEF (0x420, ARC_OPCODE_ARCALL, NONE, mpuic)
+DEF (0x421, ARC_OPCODE_ARCALL, NONE, mpufa)
+DEF (0x422, ARC_OPCODE_ARCALL, NONE, mpurdb0)
+DEF (0x423, ARC_OPCODE_ARCALL, NONE, mpurdp0)
+DEF (0x424, ARC_OPCODE_ARCALL, NONE, mpurdb1)
+DEF (0x425, ARC_OPCODE_ARCALL, NONE, mpurdp1)
+DEF (0x426, ARC_OPCODE_ARCALL, NONE, mpurdb2)
+DEF (0x427, ARC_OPCODE_ARCALL, NONE, mpurdp2)
+DEF (0x428, ARC_OPCODE_ARCALL, NONE, mpurdb3)
+DEF (0x429, ARC_OPCODE_ARCALL, NONE, mpurdp3)
+DEF (0x42a, ARC_OPCODE_ARCALL, NONE, mpurdb4)
+DEF (0x42b, ARC_OPCODE_ARCALL, NONE, mpurdp4)
+DEF (0x42c, ARC_OPCODE_ARCALL, NONE, mpurdb5)
+DEF (0x42d, ARC_OPCODE_ARCALL, NONE, mpurdp5)
+DEF (0x42e, ARC_OPCODE_ARCALL, NONE, mpurdb6)
+DEF (0x42f, ARC_OPCODE_ARCALL, NONE, mpurdp6)
+DEF (0x430, ARC_OPCODE_ARCALL, NONE, mpurdb7)
+DEF (0x431, ARC_OPCODE_ARCALL, NONE, mpurdp7)
+DEF (0x432, ARC_OPCODE_ARCALL, NONE, mpurdb8)
+DEF (0x433, ARC_OPCODE_ARCALL, NONE, mpurdp8)
+DEF (0x434, ARC_OPCODE_ARCALL, NONE, mpurdb9)
+DEF (0x435, ARC_OPCODE_ARCALL, NONE, mpurdp9)
+DEF (0x436, ARC_OPCODE_ARCALL, NONE, mpurdb10)
+DEF (0x437, ARC_OPCODE_ARCALL, NONE, mpurdp10)
+DEF (0x438, ARC_OPCODE_ARCALL, NONE, mpurdb11)
+DEF (0x439, ARC_OPCODE_ARCALL, NONE, mpurdp11)
+DEF (0x43a, ARC_OPCODE_ARCALL, NONE, mpurdb12)
+DEF (0x43b, ARC_OPCODE_ARCALL, NONE, mpurdp12)
+DEF (0x43c, ARC_OPCODE_ARCALL, NONE, mpurdb13)
+DEF (0x43d, ARC_OPCODE_ARCALL, NONE, mpurdp13)
+DEF (0x43e, ARC_OPCODE_ARCALL, NONE, mpurdb14)
+DEF (0x43f, ARC_OPCODE_ARCALL, NONE, mpurdp14)
+DEF (0x440, ARC_OPCODE_ARCALL, NONE, mpurdb15)
+DEF (0x441, ARC_OPCODE_ARCALL, NONE, mpurdp15)
+DEF (0x450, ARC_OPCODE_ARC600, NONE, pm_status)
+DEF (0x451, ARC_OPCODE_ARC600, NONE, wake)
+DEF (0x452, ARC_OPCODE_ARC600, NONE, dvfs_performance)
+DEF (0x453, ARC_OPCODE_ARC600, NONE, pwr_ctrl)
+DEF (0x460, ARC_OPCODE_ARCv2HS, NONE, tlbpd0)
+DEF (0x461, ARC_OPCODE_ARCv2HS, NONE, tlbpd1)
+DEF (0x463, ARC_OPCODE_ARCv2HS, NONE, tlbindex)
+DEF (0x464, ARC_OPCODE_ARCv2HS, NONE, tlbcommand)
+DEF (0x468, ARC_OPCODE_ARCv2HS, NONE, pid)
+DEF (0x46c, ARC_OPCODE_ARCv2HS, NONE, scratch_data0)
+DEF (0x500, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_idx)
+DEF (0x501, ARC_OPCODE_ARC700, NONE, aux_vlc_read_buf)
+DEF (0x502, ARC_OPCODE_ARC700, NONE, aux_vlc_valid_bits)
+DEF (0x503, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_in)
+DEF (0x504, ARC_OPCODE_ARC700, NONE, aux_vlc_buf_free)
+DEF (0x505, ARC_OPCODE_ARC700, NONE, aux_vlc_ibuf_status)
+DEF (0x506, ARC_OPCODE_ARC700, NONE, aux_vlc_setup)
+DEF (0x507, ARC_OPCODE_ARC700, NONE, aux_vlc_bits)
+DEF (0x508, ARC_OPCODE_ARC700, NONE, aux_vlc_table)
+DEF (0x509, ARC_OPCODE_ARC700, NONE, aux_vlc_get_symbol)
+DEF (0x50a, ARC_OPCODE_ARC700, NONE, aux_vlc_read_symbol)
+DEF (0x510, ARC_OPCODE_ARC700, NONE, aux_ucavlc_setup)
+DEF (0x511, ARC_OPCODE_ARC700, NONE, aux_ucavlc_state)
+DEF (0x512, ARC_OPCODE_ARC700, NONE, aux_cavlc_zero_left)
+DEF (0x514, ARC_OPCODE_ARC700, NONE, aux_uvlc_i_state)
+DEF (0x51c, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ptr)
+DEF (0x51d, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_end)
+DEF (0x51e, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_esc)
+DEF (0x51f, ARC_OPCODE_ARC700, NONE, aux_vlc_dma_ctrl)
+DEF (0x520, ARC_OPCODE_ARC700, NONE, aux_vlc_get_0bit)
+DEF (0x521, ARC_OPCODE_ARC700, NONE, aux_vlc_get_1bit)
+DEF (0x522, ARC_OPCODE_ARC700, NONE, aux_vlc_get_2bit)
+DEF (0x523, ARC_OPCODE_ARC700, NONE, aux_vlc_get_3bit)
+DEF (0x524, ARC_OPCODE_ARC700, NONE, aux_vlc_get_4bit)
+DEF (0x525, ARC_OPCODE_ARC700, NONE, aux_vlc_get_5bit)
+DEF (0x526, ARC_OPCODE_ARC700, NONE, aux_vlc_get_6bit)
+DEF (0x527, ARC_OPCODE_ARC700, NONE, aux_vlc_get_7bit)
+DEF (0x528, ARC_OPCODE_ARC700, NONE, aux_vlc_get_8bit)
+DEF (0x529, ARC_OPCODE_ARC700, NONE, aux_vlc_get_9bit)
+DEF (0x52a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_10bit)
+DEF (0x52b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_11bit)
+DEF (0x52c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_12bit)
+DEF (0x52d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_13bit)
+DEF (0x52e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_14bit)
+DEF (0x52f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_15bit)
+DEF (0x530, ARC_OPCODE_ARC700, NONE, aux_vlc_get_16bit)
+DEF (0x531, ARC_OPCODE_ARC700, NONE, aux_vlc_get_17bit)
+DEF (0x532, ARC_OPCODE_ARC700, NONE, aux_vlc_get_18bit)
+DEF (0x533, ARC_OPCODE_ARC700, NONE, aux_vlc_get_19bit)
+DEF (0x534, ARC_OPCODE_ARC700, NONE, aux_vlc_get_20bit)
+DEF (0x535, ARC_OPCODE_ARC700, NONE, aux_vlc_get_21bit)
+DEF (0x536, ARC_OPCODE_ARC700, NONE, aux_vlc_get_22bit)
+DEF (0x537, ARC_OPCODE_ARC700, NONE, aux_vlc_get_23bit)
+DEF (0x538, ARC_OPCODE_ARC700, NONE, aux_vlc_get_24bit)
+DEF (0x539, ARC_OPCODE_ARC700, NONE, aux_vlc_get_25bit)
+DEF (0x53a, ARC_OPCODE_ARC700, NONE, aux_vlc_get_26bit)
+DEF (0x53b, ARC_OPCODE_ARC700, NONE, aux_vlc_get_27bit)
+DEF (0x53c, ARC_OPCODE_ARC700, NONE, aux_vlc_get_28bit)
+DEF (0x53d, ARC_OPCODE_ARC700, NONE, aux_vlc_get_29bit)
+DEF (0x53e, ARC_OPCODE_ARC700, NONE, aux_vlc_get_30bit)
+DEF (0x53f, ARC_OPCODE_ARC700, NONE, aux_vlc_get_31bit)
+DEF (0x540, ARC_OPCODE_ARC700, NONE, aux_cabac_ctrl)
+DEF (0x541, ARC_OPCODE_ARC700, NONE, aux_cabac_ctx_state)
+DEF (0x542, ARC_OPCODE_ARC700, NONE, aux_cabac_cod_param)
+DEF (0x543, ARC_OPCODE_ARC700, NONE, aux_cabac_misc0)
+DEF (0x544, ARC_OPCODE_ARC700, NONE, aux_cabac_misc1)
+DEF (0x545, ARC_OPCODE_ARC700, NONE, aux_cabac_misc2)
+DEF (0x700, ARC_OPCODE_ARCALL, NONE, smart_control)
+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_0)
+DEF (0x701, ARC_OPCODE_ARC600, NONE, smart_data)
+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_2)
+DEF (0x701, ARC_OPCODE_ARC700, NONE, smart_data_3)
projects / deliverable / binutils-gdb.git / blobdiff