Remove VL variants for 4FMAPS and 4VNNIW insns.

[deliverable/binutils-gdb.git] / opcodes / arc-regs.h

diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index 0bdbd92a949ce9c80f49e5c1ed5487f85a7c8d9a..ae9bc52d6fcce7019bfbac8953db7ce9d537e119 100644 (file)
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -1,5 +1,5 @@
 /* ARC Auxiliary register definitions
-   Copyright (C) 2015-2017 Free Software Foundation, Inc.
+   Copyright (C) 2015-2018 Free Software Foundation, Inc.
 
    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
 
@@ -31,6 +31,7 @@ DEF (0x6,   ARC_OPCODE_ARCALL, NONE, pc)
 DEF (0x7,   ARC_OPCODE_ARCALL, NONE, adcr)
 DEF (0x8,   ARC_OPCODE_ARCALL, NONE, apcr)
 DEF (0x9,   ARC_OPCODE_ARCALL, NONE, acr)
+DEF (0x9,   ARC_OPCODE_ARCv2EM, NONE, sec_stat)
 DEF (0xa,   ARC_OPCODE_ARCALL, NONE, status32)
 DEF (0xb,   ARC_OPCODE_ARC600, NONE, status32_l1)
 DEF (0xb,   ARC_OPCODE_ARC700, NONE, status32_l1)
@@ -69,7 +70,6 @@ DEF (0x23,  ARC_OPCODE_ARCALL, NONE, limit0)
 DEF (0x24,  ARC_OPCODE_ARCALL, NONE, pcport)
 DEF (0x25,  ARC_OPCODE_ARCALL, NONE, int_vector_base)
 DEF (0x26,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_mode)
-DEF (0x26,  ARC_OPCODE_ARCALL, NONE, jli_base)
 DEF (0x27,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_bm0)
 DEF (0x28,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_bm1)
 DEF (0x29,  ARC_OPCODE_ARCALL, NONE, aux_vbfdw_accu)
@@ -88,9 +88,12 @@ DEF (0x35,  ARC_OPCODE_NONE,   NONE, mx1)
 DEF (0x36,  ARC_OPCODE_NONE,   NONE, my0)
 DEF (0x37,  ARC_OPCODE_NONE,   NONE, my1)
 DEF (0x38,  ARC_OPCODE_NONE,   NONE, xyconfig)
+DEF (0x38,  ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp)
 DEF (0x39,  ARC_OPCODE_NONE,   NONE, scratch_a)
+DEF (0x39,  ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp)
 DEF (0x3a,  ARC_OPCODE_NONE,   NONE, burstsys)
 DEF (0x3a,  ARC_OPCODE_NONE,   NONE, tsch)
+DEF (0x3a,  ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp)
 DEF (0x3b,  ARC_OPCODE_NONE,   NONE, burstxym)
 DEF (0x3c,  ARC_OPCODE_NONE,   NONE, burstsz)
 DEF (0x3d,  ARC_OPCODE_NONE,   NONE, burstval)
@@ -135,6 +138,7 @@ DEF (0x6d,  ARC_OPCODE_ARCALL, NONE, mpu_build)
 DEF (0x6e,  ARC_OPCODE_ARCALL, NONE, rf_build)
 DEF (0x6f,  ARC_OPCODE_ARCALL, NONE, mmu_build)
 DEF (0x70,  ARC_OPCODE_ARCALL, NONE, aa2_build)
+DEF (0x70,  ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build)
 DEF (0x71,  ARC_OPCODE_ARCALL, NONE, vecbase_build)
 DEF (0x72,  ARC_OPCODE_ARCALL, NONE, d_cache_build)
 DEF (0x73,  ARC_OPCODE_ARCALL, NONE, madi_build)
@@ -259,8 +263,11 @@ DEF (0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6)
 DEF (0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7)
 DEF (0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7)
 DEF (0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7)
+DEF (0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top)
+DEF (0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base)
 DEF (0x278, ARC_OPCODE_ARCALL, NONE, pct_control)
 DEF (0x279, ARC_OPCODE_ARCALL, NONE, pct_bank)
+DEF (0x290, ARC_OPCODE_ARCV2,  NONE, jli_base)
 DEF (0x300, ARC_OPCODE_ARCFPX, DPX,  fp_status)
 DEF (0x301, ARC_OPCODE_ARCFPX, DPX,  aux_dpfp1l)
 DEF (0x301, ARC_OPCODE_ARCFPX, DPX,  d1l)
@@ -283,6 +290,8 @@ DEF (0x403, ARC_OPCODE_ARCALL, NONE, ecr)
 DEF (0x404, ARC_OPCODE_ARCALL, NONE, efa)
 DEF (0x405, ARC_OPCODE_ARC700, NONE, tlbpd0)
 DEF (0x406, ARC_OPCODE_ARC700, NONE, tlbpd1)
+DEF (0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat)
+DEF (0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except)
 DEF (0x407, ARC_OPCODE_ARC700, NONE, tlbindex)
 DEF (0x408, ARC_OPCODE_ARC700, NONE, tlbcommand)
 DEF (0x409, ARC_OPCODE_ARC700, NONE, pid)