x86: drop stray FloatMF

[deliverable/binutils-gdb.git] / opcodes / arm-dis.c

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index ad65ffa99adff1244428f8d2931c51a0dbfa2172..033725dbad99fb93f8f9506a32f0f55c63b2ae42 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -809,8 +809,10 @@ static const struct sopcode32 coprocessor_opcodes[] =
   /* Floating point coprocessor (VFP) instructions.  */
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
-  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
     0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0ee20a10, 0x0fff0fff, "vmsr%c\tfpscr_nzcvqc, %12-15r"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -823,12 +825,22 @@ static const struct sopcode32 coprocessor_opcodes[] =
     0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
+  {ANY, ARM_FEATURE_COPROC (FPU_MVE),
+    0x0eec0a10, 0x0fff0fff, "vmsr%c\tvpr, %12-15r"},
+  {ANY, ARM_FEATURE_COPROC (FPU_MVE),
+    0x0eed0a10, 0x0fff0fff, "vmsr%c\tp0, %12-15r"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0eee0a10, 0x0fff0fff, "vmsr%c\tfpcxt_ns, %12-15r"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0eef0a10, 0x0fff0fff, "vmsr%c\tfpcxt_s, %12-15r"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
-  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+  {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_MVE),
     0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0ef20a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr_nzcvqc"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
     0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
@@ -841,6 +853,14 @@ static const struct sopcode32 coprocessor_opcodes[] =
     0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
     0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
+  {ANY, ARM_FEATURE_COPROC (FPU_MVE),
+    0x0efc0a10, 0x0fff0fff, "vmrs%c\t%12-15r, vpr"},
+  {ANY, ARM_FEATURE_COPROC (FPU_MVE),
+    0x0efd0a10, 0x0fff0fff, "vmrs%c\t%12-15r, p0"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0efe0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_ns"},
+  {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+    0x0eff0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpcxt_s"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
     0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
   {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
@@ -2999,25 +3019,25 @@ static const struct mopcode32 mve_opcodes[] =
   /* Vector VQDMLAH.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VQDMLAH,
-   0xee000e60, 0xef811f70,
+   0xee000e60, 0xff811f70,
    "vqdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
 
   /* Vector VQRDMLAH.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VQRDMLAH,
-   0xee000e40, 0xef811f70,
+   0xee000e40, 0xff811f70,
    "vqrdmlah%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
 
   /* Vector VQDMLASH.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VQDMLASH,
-   0xee001e60, 0xef811f70,
+   0xee001e60, 0xff811f70,
    "vqdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
 
   /* Vector VQRDMLASH.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
    MVE_VQRDMLASH,
-   0xee001e40, 0xef811f70,
+   0xee001e40, 0xff811f70,
    "vqrdmlash%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
 
   /* Vector VQDMLSDH.  */
@@ -6526,10 +6546,6 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
        return FALSE;
       }
 
-    case MVE_VQRDMLADH:
-    case MVE_VQDMLSDH:
-    case MVE_VQRDMLSDH:
-    case MVE_VQDMLADH:
     case MVE_VMULL_INT:
       {
        unsigned long Qd;
@@ -6599,7 +6615,7 @@ is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
              = arm_decode_field_multiple (given, 13, 15, 22, 22);
            unsigned long Qn = arm_decode_field_multiple (given, 17, 19, 7, 7);
 
-           if ((Qd == Qn))
+           if (Qd == Qn)
              {
                *unpredictable_code = UNPRED_Q_REGS_EQ_AND_SIZE_1;
                return TRUE;
@@ -6747,23 +6763,23 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
   unsigned long op1 = arm_decode_field (given, 21, 22);
   unsigned long op2 = arm_decode_field (given, 5, 6);
   unsigned long h = arm_decode_field (given, 16, 16);
-  unsigned long index, esize, targetBeat, idx;
+  unsigned long index_operand, esize, targetBeat, idx;
   void *stream = info->stream;
   fprintf_ftype func = info->fprintf_func;
 
   if ((op1 & 0x2) == 0x2)
     {
-      index = op2;
+      index_operand = op2;
       esize = 8;
     }
   else if (((op1 & 0x2) == 0x0) && ((op2 & 0x1) == 0x1))
     {
-      index = op2  >> 1;
+      index_operand = op2  >> 1;
       esize = 16;
     }
   else if (((op1 & 0x2) == 0) && ((op2 & 0x3) == 0))
     {
-      index = 0;
+      index_operand = 0;
       esize = 32;
     }
   else
@@ -6773,7 +6789,7 @@ print_mve_vmov_index (struct disassemble_info *info, unsigned long given)
     }
 
   targetBeat =  (op1 & 0x1) | (h << 1);
-  idx = index + targetBeat * (32/esize);
+  idx = index_operand + targetBeat * (32/esize);
 
   func (stream, "%lu", idx);
 }