MA 02110-1301, USA. */
#include "sysdep.h"
+#include <assert.h>
#include "disassemble.h"
#include "opcode/arm.h"
bfd_vma last_mapping_addr;
};
+enum mve_instructions
+{
+ MVE_VPST,
+ MVE_VPT_FP_T1,
+ MVE_VPT_FP_T2,
+ MVE_VPT_VEC_T1,
+ MVE_VPT_VEC_T2,
+ MVE_VPT_VEC_T3,
+ MVE_VPT_VEC_T4,
+ MVE_VPT_VEC_T5,
+ MVE_VPT_VEC_T6,
+ MVE_VCMP_FP_T1,
+ MVE_VCMP_FP_T2,
+ MVE_VCMP_VEC_T1,
+ MVE_VCMP_VEC_T2,
+ MVE_VCMP_VEC_T3,
+ MVE_VCMP_VEC_T4,
+ MVE_VCMP_VEC_T5,
+ MVE_VCMP_VEC_T6,
+ MVE_VDUP,
+ MVE_VEOR,
+ MVE_VFMAS_FP_SCALAR,
+ MVE_VFMA_FP_SCALAR,
+ MVE_VFMA_FP,
+ MVE_VFMS_FP,
+ MVE_VHADD_T1,
+ MVE_VHADD_T2,
+ MVE_VHSUB_T1,
+ MVE_VHSUB_T2,
+ MVE_VRHADD,
+ MVE_VLD2,
+ MVE_VLD4,
+ MVE_VST2,
+ MVE_VST4,
+ MVE_VLDRB_T1,
+ MVE_VLDRH_T2,
+ MVE_VLDRB_T5,
+ MVE_VLDRH_T6,
+ MVE_VLDRW_T7,
+ MVE_VSTRB_T1,
+ MVE_VSTRH_T2,
+ MVE_VSTRB_T5,
+ MVE_VSTRH_T6,
+ MVE_VSTRW_T7,
+ MVE_NONE
+};
+
+enum mve_unpredictable
+{
+ UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
+ */
+ UNPRED_FCA_0_FCB_1, /* Unpredictable because fcA = 0 and
+ fcB = 1 (vpt). */
+ UNPRED_R13, /* Unpredictable because r13 (sp) or
+ r15 (sp) used. */
+ UNPRED_R15, /* Unpredictable because r15 (pc) is used. */
+ UNPRED_Q_GT_4, /* Unpredictable because
+ vec reg start > 4 (vld4/st4). */
+ UNPRED_Q_GT_6, /* Unpredictable because
+ vec reg start > 6 (vld2/st2). */
+ UNPRED_R13_AND_WB, /* Unpredictable becase gp reg = r13
+ and WB bit = 1. */
+ UNPRED_NONE /* No unpredictable behavior. */
+};
+
+enum mve_undefined
+{
+ UNDEF_SIZE_3, /* undefined because size == 3. */
+ UNDEF_SIZE_3, /* undefined because size == 3. */
+ UNDEF_SIZE_LE_1, /* undefined because size <= 1. */
+ UNDEF_NONE /* no undefined behavior. */
+};
+
struct opcode32
{
arm_feature_set arch; /* Architecture defining this insn. */
const char * assembler; /* How to disassemble this insn. */
};
+/* MVE opcodes. */
+
+struct mopcode32
+{
+ arm_feature_set arch; /* Architecture defining this insn. */
+ enum mve_instructions mve_op; /* Specific mve instruction for faster
+ decoding. */
+ unsigned long value; /* If arch is 0 then value is a sentinel. */
+ unsigned long mask; /* Recognise insn if (op & mask) == value. */
+ const char * assembler; /* How to disassemble this insn. */
+};
+
+enum isa {
+ ANY,
+ T32,
+ ARM
+};
+
+
+/* Shared (between Arm and Thumb mode) opcode. */
+struct sopcode32
+{
+ enum isa isa; /* Execution mode instruction availability. */
+ arm_feature_set arch; /* Architecture defining this insn. */
+ unsigned long value; /* If arch is 0 then value is a sentinel. */
+ unsigned long mask; /* Recognise insn if (op & mask) == value. */
+ const char * assembler; /* How to disassemble this insn. */
+};
+
struct opcode16
{
arm_feature_set arch; /* Architecture defining this insn. */
UNPREDICTABLE if not AL in Thumb)
%A print address for ldc/stc/ldf/stf instruction
%B print vstm/vldm register list
+ %C print vscclrm register list
%I print cirrus signed shift immediate: bits 0..3|4..6
+ %J print register for VLDR instruction
+ %K print address for VLDR instruction
%F print the COUNT field of a LFM/SFM instruction.
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
/* Common coprocessor opcodes shared between Arm and Thumb-2. */
-static const struct opcode32 coprocessor_opcodes[] =
+static const struct sopcode32 coprocessor_opcodes[] =
{
/* XScale instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0ff0,
"mia%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0ff0,
"miaph%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
/* Intel Wireless MMX technology instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
- {ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_IWMMXT_START, 0, "" },
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e800120, 0x0f800ff0,
"wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000a0, 0x0f800ff0,
"wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
- {ARM_FEATURE_CORE_LOW (0),
+ {ANY, ARM_FEATURE_CORE_LOW (0),
SENTINEL_IWMMXT_END, 0, "" },
/* Floating point coprocessor (FPA) instructions. */
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V1),
0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
- {ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
+ /* Armv8.1-M Mainline instructions. */
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0b00, 0xffbf0f01, "vscclrm%c\t%C"},
+ {T32, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xec9f0a00, 0xffbf0f00, "vscclrm%c\t%C"},
+
/* ARMv8-M Mainline Security Extensions instructions. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
/* Register load/store. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
+ {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+ 0xec100f80, 0xfe101f80, "vldr%c\t%J, %K"},
+ {ANY, ARM_FEATURE_COPROC (ARM_EXT2_V8_1M_MAIN),
+ 0xec000f80, 0xfe101f80, "vstr%c\t%J, %K"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
/* Data transfer between ARM and NEON registers. */
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
- 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
/* Half-precision conversion instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb20b40, 0x0fbf0f50, "vcvt%7?tb%c.f64.f16\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb30b40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16),
0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
/* Floating point coprocessor (VFP) instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD),
0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V3),
0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19E"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V2),
0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
- {ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
+ {ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
/* VFP Fused multiply add instructions. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
/* FP v5. */
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000a00, 0xff800f50, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe000b00, 0xff800f50, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a00, 0xffb00f50, "vmaxnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b00, 0xffb00f50, "vmaxnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800a40, 0xffb00f50, "vminnm%u.f32\t%y1, %y2, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfe800b40, 0xffb00f50, "vminnm%u.f64\t%z1, %z2, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0a40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfebc0b40, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f64\t%y1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60a40, 0x0fbe0f50, "vrint%7,16??xzr%c.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0x0eb60b40, 0x0fbe0f50, "vrint%7,16??xzr%c.f64\t%z1, %z0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80a40, 0xffbc0fd0, "vrint%16-17?mpna%u.f32\t%y1, %y0"},
- {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
+ {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
0xfeb80b40, 0xffbc0fd0, "vrint%16-17?mpna%u.f64\t%z1, %z0"},
/* Generic coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (0), SENTINEL_GENERIC_START, 0, "" },
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5E),
0x0c500000, 0x0ff00000,
"mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000000, 0x0f000010,
"cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e10f010, 0x0f10f010,
"mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e100010, 0x0f100010,
"mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0e000010, 0x0f100010,
"mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V2),
0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
/* V6 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc500000, 0xfff00000,
"mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
0xfc400000, 0xfff00000,
"mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
/* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
/* Dot Product instructions in the space of coprocessor 13. */
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
- {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
+ {ANY, ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
/* ARMv8.2 FMAC Long instructions in the space of coprocessor 8. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-3d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfc200850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfca00850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-3,5d"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000810, 0xffb00f50, "vfmal.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100810, 0xffb00f50, "vfmsl.f16\t%12-15,22D, s%7,16-19d, s%5,0-2d[%3d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe000850, 0xffb00f50, "vfmal.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_V8_2A),
0xfe100850, 0xffb00f50, "vfmsl.f16\t%12-15,22Q, d%16-19,7d, d%0-2d[%3,5d]"},
/* V5 coprocessor instructions. */
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000000, 0xff000010,
"cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe000010, 0xff100010,
"mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ {ANY, ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
0xfe100010, 0xff100010,
"mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
/* ARMv8.2 half-precision Floating point coprocessor 9 (VFP) instructions.
cp_num: bit <11:8> == 0b1001.
cond: bit <31:28> == 0b1110, otherwise, it's UNPREDICTABLE. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb009c0, 0x0fbf0fd0, "vabs%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300900, 0x0fb00f50, "vadd%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb40940, 0x0fbf0f50, "vcmp%7'e%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb50940, 0x0fbf0f70, "vcmp%7'e%c.f16\t%y1, #0.0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eba09c0, 0x0fbe0fd0, "vcvt%c.f16.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebe09c0, 0x0fbe0fd0, "vcvt%c.%16?us%7?31%7?26.f16\t%y1, %y1, #%5,0-3k"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ebc0940, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb80940, 0x0fbf0f50, "vcvt%c.f16.%7?su32\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfebc0940, 0xffbc0f50, "vcvt%16-17?mpna%u.%7?su32.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e800900, 0x0fb00f50, "vdiv%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00900, 0x0fb00f50, "vfma%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0ea00940, 0x0fb00f50, "vfms%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900940, 0x0fb00f50, "vfnma%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e900900, 0x0fb00f50, "vfnms%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00ac0, 0xffbf0fd0, "vins.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb00a40, 0xffbf0fd0, "vmovx%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d100900, 0x0f300f00, "vldr%c.16\t%y1, %A"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0d000900, 0x0f300f00, "vstr%c.16\t%y1, %A"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800900, 0xffb00f50, "vmaxnm%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe800940, 0xffb00f50, "vminnm%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000900, 0x0fb00f50, "vmla%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000940, 0x0fb00f50, "vmls%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100910, 0x0ff00f7f, "vmov%c.f16\t%12-15r, %y2"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e000910, 0x0ff00f7f, "vmov%c.f16\t%y2, %12-15r"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xeb00900, 0x0fb00ff0, "vmov%c.f16\t%y1, #%0-3,16-19E"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200900, 0x0fb00f50, "vmul%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb10940, 0x0fbf0fd0, "vneg%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100940, 0x0fb00f50, "vnmla%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e100900, 0x0fb00f50, "vnmls%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e200940, 0x0fb00f50, "vnmul%c.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb60940, 0x0fbe0f50, "vrint%7,16??xzr%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfeb80940, 0xffbc0fd0, "vrint%16-17?mpna%u.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0xfe000900, 0xff800f50, "vsel%20-21c%u.f16\t%y1, %y2, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0eb109c0, 0x0fbf0fd0, "vsqrt%c.f16\t%y1, %y0"},
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
/* ARMv8.3 javascript conversion instruction. */
- {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
+ {ANY, ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
- {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
+ {ANY, ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
};
/* Neon opcode table: This does not encode the top byte -- that is
0xf2b00000, 0xffb00810,
"vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
+ /* Data transfer between ARM and NEON registers. */
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
+ 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
+
/* Move data element to all lanes. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_V1),
0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
{ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
};
+/* mve opcode table. */
+
+/* print_insn_mve recognizes the following format control codes:
+
+ %% %
+
+ %c print condition code
+ %d print addr mode of MVE vldr[bhw] and vstr[bhw]
+ %u print 'U' (unsigned) or 'S' for various mve instructions
+ %i print MVE predicate(s) for vpt and vpst
+ %n print vector comparison code for predicated instruction
+ %v print vector predicate for instruction in predicated
+ block
+ %w print writeback mode for MVE v{st,ld}[24]
+ %B print v{st,ld}[24] any one operands
+
+ %<bitfield>r print as an ARM register
+ %<bitfield>d print the bitfield in decimal
+ %<bitfield>Q print as a MVE Q register
+ %<bitfield>Z as %<>r but r15 is ZR instead of PC and r13 is
+ UNPREDICTABLE
+ %<bitfield>s print size for vector predicate & non VMOV instructions
+*/
+
+static const struct mopcode32 mve_opcodes[] =
+{
+ /* MVE. */
+
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPST,
+ 0xfe310f4d, 0xffbf1fff,
+ "vpst%i"
+ },
+
+ /* Floating point VPT T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VPT_FP_T1,
+ 0xee310f00, 0xefb10f50,
+ "vpt%i.f%28s\t%n, %17-19Q, %1-3,5Q"},
+ /* Floating point VPT T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VPT_FP_T2,
+ 0xee310f40, 0xefb10f50,
+ "vpt%i.f%28s\t%n, %17-19Q, %0-3Z"},
+
+ /* Vector VPT T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T1,
+ 0xfe010f00, 0xff811f51,
+ "vpt%i.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VPT T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T2,
+ 0xfe010f01, 0xff811f51,
+ "vpt%i.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VPT T3. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T3,
+ 0xfe011f00, 0xff811f50,
+ "vpt%i.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VPT T4. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T4,
+ 0xfe010f40, 0xff811f70,
+ "vpt%i.i%20-21s\t%n, %17-19Q, %0-3Z"},
+ /* Vector VPT T5. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T5,
+ 0xfe010f60, 0xff811f70,
+ "vpt%i.u%20-21s\t%n, %17-19Q, %0-3Z"},
+ /* Vector VPT T6. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VPT_VEC_T6,
+ 0xfe011f40, 0xff811f50,
+ "vpt%i.s%20-21s\t%n, %17-19Q, %0-3Z"},
+
+ /* Vector VCMP floating point T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCMP_FP_T1,
+ 0xee310f00, 0xeff1ef50,
+ "vcmp%v.f%28s\t%n, %17-19Q, %1-3,5Q"},
+
+ /* Vector VCMP floating point T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VCMP_FP_T2,
+ 0xee310f40, 0xeff1ef50,
+ "vcmp%v.f%28s\t%n, %17-19Q, %0-3Z"},
+
+ /* Vector VCMP T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T1,
+ 0xfe010f00, 0xffc1ff51,
+ "vcmp%v.i%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VCMP T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T2,
+ 0xfe010f01, 0xffc1ff51,
+ "vcmp%v.u%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VCMP T3. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T3,
+ 0xfe011f00, 0xffc1ff50,
+ "vcmp%v.s%20-21s\t%n, %17-19Q, %1-3,5Q"},
+ /* Vector VCMP T4. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T4,
+ 0xfe010f40, 0xffc1ff70,
+ "vcmp%v.i%20-21s\t%n, %17-19Q, %0-3Z"},
+ /* Vector VCMP T5. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T5,
+ 0xfe010f60, 0xffc1ff70,
+ "vcmp%v.u%20-21s\t%n, %17-19Q, %0-3Z"},
+ /* Vector VCMP T6. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VCMP_VEC_T6,
+ 0xfe011f40, 0xffc1ff50,
+ "vcmp%v.s%20-21s\t%n, %17-19Q, %0-3Z"},
+
+ /* Vector VDUP. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VDUP,
+ 0xeea00b10, 0xffb10f5f,
+ "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
+
+ /* Vector VEOR. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VEOR,
+ 0xff000150, 0xffd11f51,
+ "veor%v\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VFMA, vector * scalar. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VFMA_FP_SCALAR,
+ 0xee310e40, 0xefb11f70,
+ "vfma%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VFMA floating point. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VFMA_FP,
+ 0xef000c50, 0xffa11f51,
+ "vfma%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VFMS floating point. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VFMS_FP,
+ 0xef200c50, 0xffa11f51,
+ "vfms%v.f%20s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VFMAS, vector * scalar. */
+ {ARM_FEATURE_COPROC (FPU_MVE_FP),
+ MVE_VFMAS_FP_SCALAR,
+ 0xee311e40, 0xefb11f70,
+ "vfmas%v.f%28s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VHADD T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VHADD_T1,
+ 0xef000040, 0xef811f51,
+ "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VHADD T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VHADD_T2,
+ 0xee000f40, 0xef811f70,
+ "vhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VHSUB T1. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VHSUB_T1,
+ 0xef000240, 0xef811f51,
+ "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VHSUB T2. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VHSUB_T2,
+ 0xee001f40, 0xef811f70,
+ "vhsub%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %0-3r"},
+
+ /* Vector VDUP. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VDUP,
+ 0xeea00b10, 0xffb10f5f,
+ "vdup%v.%5,22s\t%17-19,7Q, %12-15r"},
+
+ /* Vector VRHADD. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VRHADD,
+ 0xef000140, 0xef811f51,
+ "vrhadd%v.%u%20-21s\t%13-15,22Q, %17-19,7Q, %1-3,5Q"},
+
+ /* Vector VLD2. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLD2,
+ 0xfc901e00, 0xff901e5f,
+ "vld2%5d.%7-8s\t%B, [%16-19r]%w"},
+
+ /* Vector VLD4. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLD4,
+ 0xfc901e01, 0xff901e1f,
+ "vld4%5-6d.%7-8s\t%B, [%16-19r]%w"},
+
+ /* Vector VLDRB. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLDRB_T1,
+ 0xec100e00, 0xee581e00,
+ "vldrb%v.%u%7-8s\t%13-15Q, %d"},
+
+ /* Vector VLDRH. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLDRH_T2,
+ 0xec180e00, 0xee581e00,
+ "vldrh%v.%u%7-8s\t%13-15Q, %d"},
+
+ /* Vector VLDRB unsigned, variant T5. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLDRB_T5,
+ 0xec101e00, 0xfe101f80,
+ "vldrb%v.u8\t%13-15,22Q, %d"},
+
+ /* Vector VLDRH unsigned, variant T6. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLDRH_T6,
+ 0xec101e80, 0xfe101f80,
+ "vldrh%v.u16\t%13-15,22Q, %d"},
+
+ /* Vector VLDRW unsigned, variant T7. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VLDRW_T7,
+ 0xec101f00, 0xfe101f80,
+ "vldrw%v.u32\t%13-15,22Q, %d"},
+
+ /* Vector VST2 no writeback. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VST2,
+ 0xfc801e00, 0xffb01e5f,
+ "vst2%5d.%7-8s\t%B, [%16-19r]"},
+
+ /* Vector VST2 writeback. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VST2,
+ 0xfca01e00, 0xffb01e5f,
+ "vst2%5d.%7-8s\t%B, [%16-19r]!"},
+
+ /* Vector VST4 no writeback. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VST4,
+ 0xfc801e01, 0xffb01e1f,
+ "vst4%5-6d.%7-8s\t%B, [%16-19r]"},
+
+ /* Vector VST4 writeback. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VST4,
+ 0xfca01e01, 0xffb01e1f,
+ "vst4%5-6d.%7-8s\t%B, [%16-19r]!"},
+
+ /* Vector VSTRB. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VSTRB_T1,
+ 0xec000e00, 0xfe581e00,
+ "vstrb%v.%7-8s\t%13-15Q, %d"},
+
+ /* Vector VSTRH. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VSTRH_T2,
+ 0xec080e00, 0xfe581e00,
+ "vstrh%v.%7-8s\t%13-15Q, %d"},
+
+ /* Vector VSTRB variant T5. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VSTRB_T5,
+ 0xec001e00, 0xfe101f80,
+ "vstrb%v.8\t%13-15,22Q, %d"},
+
+ /* Vector VSTRH variant T6. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VSTRH_T6,
+ 0xec001e80, 0xfe101f80,
+ "vstrh%v.16\t%13-15,22Q, %d"},
+
+ /* Vector VSTRW variant T7. */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VSTRW_T7,
+ 0xec001f00, 0xfe101f80,
+ "vstrw%v.32\t%13-15,22Q, %d"},
+
+ {ARM_FEATURE_CORE_LOW (0),
+ MVE_NONE,
+ 0x00000000, 0x00000000, 0}
+};
+
/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
ordered: they must be searched linearly from the top to obtain a correct
match. */
%a print the address of a plain load/store
%w print the width and signedness of a core load/store
%m print register mask for ldm/stm
+ %n print register mask for clrm
%E print the lsb and width fields of a bfc/bfi instruction
%F print the lsb and width fields of a sbfx/ubfx instruction
+ %G print a fallback offset for Branch Future instructions
+ %W print an offset for BF instruction
+ %Y print an offset for BFL instruction
+ %Z print an offset for BFCSEL instruction
+ %Q print an offset for Low Overhead Loop instructions
+ %P print an offset for Low Overhead Loop end instructions
%b print a conditional branch offset
%B print an unconditional branch offset
%s print the shift field of an SSAT instruction
%<bitfield>W print bitfield*4 in decimal
%<bitfield>r print bitfield as an ARM register
%<bitfield>R as %<>r but r15 is UNPREDICTABLE
+ %<bitfield>S as %<>r but r13 and r15 is UNPREDICTABLE
%<bitfield>c print bitfield as a condition code
%<bitfield>'c print specified char iff bitfield is all ones
makes heavy use of special-case bit patterns. */
static const struct opcode32 thumb32_opcodes[] =
{
+ /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
+ instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040c001, 0xfff0f001, "wls\tlr, %16-19S, %Q"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xfff0ffff, "dls\tlr, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf02fc001, 0xfffff001, "le\t%P"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf00fc001, 0xfffff001, "le\tlr, %P"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf040e001, 0xf860f001, "bf%c\t%G, %W"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000c001, 0xf800f001, "bfl%c\t%G, %Y"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xf000e001, 0xf840f001, "bfcsel\t%G, %Z, %18-21c"},
+
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
+ 0xe89f0000, 0xffff2000, "clrm%c\t%n"},
+
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
"wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
};
+static const char *const vec_condnames[] =
+{ "eq", "ne", "cs", "hi", "ge", "lt", "gt", "le"
+};
+
+static const char *const mve_predicatenames[] =
+{ "", "ttt", "tt", "tte", "t", "tee", "te", "tet", "",
+ "eee", "ee", "eet", "e", "ett", "et", "ete"
+};
+
+/* Names for 2-bit size field for mve vector isntructions. */
+static const char *const mve_vec_sizename[] =
+ { "8", "16", "32", "64"};
+
+/* Indicates whether we are processing a then predicate,
+ else predicate or none at all. */
+enum vpt_pred_state
+{
+ PRED_NONE,
+ PRED_THEN,
+ PRED_ELSE
+};
+
+/* Information used to process a vpt block and subsequent instructions. */
+struct vpt_block
+{
+ /* Are we in a vpt block. */
+ bfd_boolean in_vpt_block;
+
+ /* Next predicate state if in vpt block. */
+ enum vpt_pred_state next_pred_state;
+
+ /* Mask from vpt/vpst instruction. */
+ long predicate_mask;
+
+ /* Instruction number in vpt block. */
+ long current_insn_num;
+
+ /* Number of instructions in vpt block.. */
+ long num_pred_insn;
+};
+
+static struct vpt_block vpt_block_state =
+{
+ FALSE,
+ PRED_NONE,
+ 0,
+ 0,
+ 0
+};
+
/* Default to GCC register name set. */
static unsigned int regname_selected = 1;
\f
/* Functions. */
+/* Extract the predicate mask for a VPT or VPST instruction.
+ The mask is composed of bits 13-15 (Mkl) and bit 22 (Mkh). */
+
+static long
+mve_extract_pred_mask (long given)
+{
+ return ((given & 0x00400000) >> 19) | ((given & 0xe000) >> 13);
+}
+
+/* Return the number of instructions in a MVE predicate block. */
+static long
+num_instructions_vpt_block (long given)
+{
+ long mask = mve_extract_pred_mask (given);
+ if (mask == 0)
+ return 0;
+
+ if (mask == 8)
+ return 1;
+
+ if ((mask & 7) == 4)
+ return 2;
+
+ if ((mask & 3) == 2)
+ return 3;
+
+ if ((mask & 1) == 1)
+ return 4;
+
+ return 0;
+}
+
+static void
+mark_outside_vpt_block (void)
+{
+ vpt_block_state.in_vpt_block = FALSE;
+ vpt_block_state.next_pred_state = PRED_NONE;
+ vpt_block_state.predicate_mask = 0;
+ vpt_block_state.current_insn_num = 0;
+ vpt_block_state.num_pred_insn = 0;
+}
+
+static void
+mark_inside_vpt_block (long given)
+{
+ vpt_block_state.in_vpt_block = TRUE;
+ vpt_block_state.next_pred_state = PRED_THEN;
+ vpt_block_state.predicate_mask = mve_extract_pred_mask (given);
+ vpt_block_state.current_insn_num = 0;
+ vpt_block_state.num_pred_insn = num_instructions_vpt_block (given);
+ assert (vpt_block_state.num_pred_insn >= 1);
+}
+
+static enum vpt_pred_state
+invert_next_predicate_state (enum vpt_pred_state astate)
+{
+ if (astate == PRED_THEN)
+ return PRED_ELSE;
+ else if (astate == PRED_ELSE)
+ return PRED_THEN;
+ else
+ return PRED_NONE;
+}
+
+static enum vpt_pred_state
+update_next_predicate_state (void)
+{
+ long pred_mask = vpt_block_state.predicate_mask;
+ long mask_for_insn = 0;
+
+ switch (vpt_block_state.current_insn_num)
+ {
+ case 1:
+ mask_for_insn = 8;
+ break;
+
+ case 2:
+ mask_for_insn = 4;
+ break;
+
+ case 3:
+ mask_for_insn = 2;
+ break;
+
+ case 4:
+ return PRED_NONE;
+ }
+
+ if (pred_mask & mask_for_insn)
+ return invert_next_predicate_state (vpt_block_state.next_pred_state);
+ else
+ return vpt_block_state.next_pred_state;
+}
+
+static void
+update_vpt_block_state (void)
+{
+ vpt_block_state.current_insn_num++;
+ if (vpt_block_state.current_insn_num == vpt_block_state.num_pred_insn)
+ {
+ /* No more instructions to process in vpt block. */
+ mark_outside_vpt_block ();
+ return;
+ }
+
+ vpt_block_state.next_pred_state = update_next_predicate_state ();
+}
/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
Returns pointer to following character of the format string and
}
}
-#define W_BIT 21
-#define I_BIT 22
-#define U_BIT 23
-#define P_BIT 24
-
-#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
-#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
-#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
-#define PRE_BIT_SET (given & (1 << P_BIT))
+/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
-/* Print one coprocessor instruction on INFO->STREAM.
- Return TRUE if the instuction matched, FALSE if this is not a
- recognised coprocessor instruction. */
+static bfd_boolean
+is_mve_okay_in_it (enum mve_instructions matched_insn)
+{
+ return FALSE;
+}
static bfd_boolean
-print_insn_coprocessor (bfd_vma pc,
- struct disassemble_info *info,
- long given,
- bfd_boolean thumb)
+is_mve_architecture (struct disassemble_info *info)
{
- const struct opcode32 *insn;
- void *stream = info->stream;
- fprintf_ftype func = info->fprintf_func;
- unsigned long mask;
- unsigned long value = 0;
- int cond;
- int cp_num;
struct arm_private_data *private_data = info->private_data;
- arm_feature_set allowed_arches = ARM_ARCH_NONE;
+ arm_feature_set allowed_arches = private_data->features;
- allowed_arches = private_data->features;
+ arm_feature_set arm_ext_v8_1m_main
+ = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
- for (insn = coprocessor_opcodes; insn->assembler; insn++)
- {
- unsigned long u_reg = 16;
- bfd_boolean is_unpredictable = FALSE;
- signed long value_in_comment = 0;
- const char *c;
+ if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
+ && !ARM_CPU_IS_ANY (allowed_arches))
+ return TRUE;
+ else
+ return FALSE;
+}
- if (ARM_FEATURE_ZERO (insn->arch))
- switch (insn->value)
- {
- case SENTINEL_IWMMXT_START:
- if (info->mach != bfd_mach_arm_XScale
- && info->mach != bfd_mach_arm_iWMMXt
- && info->mach != bfd_mach_arm_iWMMXt2)
- do
- insn++;
- while ((! ARM_FEATURE_ZERO (insn->arch))
- && insn->value != SENTINEL_IWMMXT_END);
- continue;
+static bfd_boolean
+is_vpt_instruction (long given)
+{
- case SENTINEL_IWMMXT_END:
- continue;
+ /* If mkh:mkl is '0000' then its not a vpt/vpst instruction. */
+ if ((given & 0x0040e000) == 0)
+ return FALSE;
- case SENTINEL_GENERIC_START:
- allowed_arches = private_data->features;
- continue;
+ /* VPT floating point T1 variant. */
+ if (((given & 0xefb10f50) == 0xee310f00 && ((given & 0x1001) != 0x1))
+ /* VPT floating point T2 variant. */
+ || ((given & 0xefb10f50) == 0xee310f40)
+ /* VPT vector T1 variant. */
+ || ((given & 0xff811f51) == 0xfe010f00)
+ /* VPT vector T2 variant. */
+ || ((given & 0xff811f51) == 0xfe010f01
+ && ((given & 0x300000) != 0x300000))
+ /* VPT vector T3 variant. */
+ || ((given & 0xff811f50) == 0xfe011f00)
+ /* VPT vector T4 variant. */
+ || ((given & 0xff811f70) == 0xfe010f40)
+ /* VPT vector T5 variant. */
+ || ((given & 0xff811f70) == 0xfe010f60)
+ /* VPT vector T6 variant. */
+ || ((given & 0xff811f50) == 0xfe011f40)
+ /* VPST vector T variant. */
+ || ((given & 0xffbf1fff) == 0xfe310f4d))
+ return TRUE;
+ else
+ return FALSE;
+}
- default:
- abort ();
- }
+/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
+ and ending bitfield = END. END must be greater than START. */
- mask = insn->mask;
- value = insn->value;
- cp_num = (given >> 8) & 0xf;
+static unsigned long
+arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
+{
+ int bits = end - start;
- if (thumb)
- {
- /* The high 4 bits are 0xe for Arm conditional instructions, and
- 0xe for arm unconditional instructions. The rest of the
- encoding is the same. */
+ if (bits < 0)
+ abort ();
+
+ return ((given >> start) & ((2ul << bits) - 1));
+}
+
+/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
+ START:END and START2:END2. END/END2 must be greater than
+ START/START2. */
+
+static unsigned long
+arm_decode_field_multiple (unsigned long given, unsigned int start,
+ unsigned int end, unsigned int start2,
+ unsigned int end2)
+{
+ int bits = end - start;
+ int bits2 = end2 - start2;
+ unsigned long value = 0;
+ int width = 0;
+
+ if (bits2 < 0)
+ abort ();
+
+ value = arm_decode_field (given, start, end);
+ width += bits + 1;
+
+ value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
+ return value;
+}
+
+/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
+ This helps us decode instructions that change mnemonic depending on specific
+ operand values/encodings. */
+
+static bfd_boolean
+is_mve_encoding_conflict (unsigned long given,
+ enum mve_instructions matched_insn)
+{
+ switch (matched_insn)
+ {
+ case MVE_VPST:
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VPT_FP_T1:
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
+ return TRUE;
+ if ((arm_decode_field (given, 12, 12) == 0)
+ && (arm_decode_field (given, 0, 0) == 1))
+ return TRUE;
+ return FALSE;
+
+ case MVE_VPT_FP_T2:
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
+ return TRUE;
+ if (arm_decode_field (given, 0, 3) == 0xd)
+ return TRUE;
+ return FALSE;
+
+ case MVE_VPT_VEC_T1:
+ case MVE_VPT_VEC_T2:
+ case MVE_VPT_VEC_T3:
+ case MVE_VPT_VEC_T4:
+ case MVE_VPT_VEC_T5:
+ case MVE_VPT_VEC_T6:
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) == 0)
+ return TRUE;
+ if (arm_decode_field (given, 20, 21) == 3)
+ return TRUE;
+ return FALSE;
+
+ case MVE_VCMP_FP_T1:
+ if ((arm_decode_field (given, 12, 12) == 0)
+ && (arm_decode_field (given, 0, 0) == 1))
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VCMP_FP_T2:
+ if (arm_decode_field (given, 0, 3) == 0xd)
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VHADD_T2:
+ case MVE_VHSUB_T2:
+ case MVE_VCMP_VEC_T1:
+ case MVE_VCMP_VEC_T2:
+ case MVE_VCMP_VEC_T3:
+ case MVE_VCMP_VEC_T4:
+ case MVE_VCMP_VEC_T5:
+ case MVE_VCMP_VEC_T6:
+ if (arm_decode_field (given, 20, 21) == 3)
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VLD2:
+ case MVE_VLD4:
+ case MVE_VST2:
+ case MVE_VST4:
+ if (arm_decode_field (given, 7, 8) == 3)
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VSTRB_T1:
+ case MVE_VSTRH_T2:
+ if ((arm_decode_field (given, 24, 24) == 0)
+ && (arm_decode_field (given, 21, 21) == 0))
+ {
+ return TRUE;
+ }
+ else if ((arm_decode_field (given, 7, 8) == 3))
+ return TRUE;
+ else
+ return FALSE;
+
+ case MVE_VSTRB_T5:
+ case MVE_VSTRH_T6:
+ case MVE_VSTRW_T7:
+ if ((arm_decode_field (given, 24, 24) == 0)
+ && (arm_decode_field (given, 21, 21) == 0))
+ {
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ default:
+ return FALSE;
+
+ }
+}
+
+static void
+print_mve_vld_str_addr (struct disassemble_info *info,
+ unsigned long given,
+ enum mve_instructions matched_insn)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ unsigned long p, w, gpr, imm, add, mod_imm;
+
+ imm = arm_decode_field (given, 0, 6);
+ mod_imm = imm;
+
+ switch (matched_insn)
+ {
+ case MVE_VLDRB_T1:
+ case MVE_VSTRB_T1:
+ gpr = arm_decode_field (given, 16, 18);
+ break;
+
+ case MVE_VLDRH_T2:
+ case MVE_VSTRH_T2:
+ gpr = arm_decode_field (given, 16, 18);
+ mod_imm = imm << 1;
+ break;
+
+ case MVE_VLDRH_T6:
+ case MVE_VSTRH_T6:
+ gpr = arm_decode_field (given, 16, 19);
+ mod_imm = imm << 1;
+ break;
+
+ case MVE_VLDRW_T7:
+ case MVE_VSTRW_T7:
+ gpr = arm_decode_field (given, 16, 19);
+ mod_imm = imm << 2;
+ break;
+
+ case MVE_VLDRB_T5:
+ case MVE_VSTRB_T5:
+ gpr = arm_decode_field (given, 16, 19);
+ break;
+
+ default:
+ return;
+ }
+
+ p = arm_decode_field (given, 24, 24);
+ w = arm_decode_field (given, 21, 21);
+
+ add = arm_decode_field (given, 23, 23);
+
+ char * add_sub;
+
+ /* Don't print anything for '+' as it is implied. */
+ if (add == 1)
+ add_sub = "";
+ else
+ add_sub = "-";
+
+ if (p == 1)
+ {
+ /* Offset mode. */
+ if (w == 0)
+ func (stream, "[%s, #%s%lu]", arm_regnames[gpr], add_sub, mod_imm);
+ /* Pre-indexed mode. */
+ else
+ func (stream, "[%s, #%s%lu]!", arm_regnames[gpr], add_sub, mod_imm);
+ }
+ else if ((p == 0) && (w == 1))
+ /* Post-index mode. */
+ func (stream, "[%s], #%s%lu", arm_regnames[gpr], add_sub, mod_imm);
+}
+
+/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
+ Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
+ this encoding is undefined. */
+
+static bfd_boolean
+is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
+ enum mve_undefined *undefined_code)
+{
+ *undefined_code = UNDEF_NONE;
+
+ switch (matched_insn)
+ {
+ case MVE_VDUP:
+ if (arm_decode_field_multiple (given, 5, 5, 22, 22) == 3)
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VRHADD:
+ case MVE_VHADD_T1:
+ case MVE_VHSUB_T1:
+ if (arm_decode_field (given, 20, 21) == 3)
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VLDRB_T1:
+ if (arm_decode_field (given, 7, 8) == 3)
+ {
+ *undefined_code = UNDEF_SIZE_3;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VLDRH_T2:
+ if (arm_decode_field (given, 7, 8) <= 1)
+ {
+ *undefined_code = UNDEF_SIZE_LE_1;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VSTRB_T1:
+ if ((arm_decode_field (given, 7, 8) == 0))
+ {
+ *undefined_code = UNDEF_SIZE_0;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VSTRH_T2:
+ if ((arm_decode_field (given, 7, 8) <= 1))
+ {
+ *undefined_code = UNDEF_SIZE_LE_1;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ default:
+ return FALSE;
+ }
+}
+
+/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
+ Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
+ why this encoding is unpredictable. */
+
+static bfd_boolean
+is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
+ enum mve_unpredictable *unpredictable_code)
+{
+ *unpredictable_code = UNPRED_NONE;
+
+ switch (matched_insn)
+ {
+ case MVE_VCMP_FP_T2:
+ case MVE_VPT_FP_T2:
+ if ((arm_decode_field (given, 12, 12) == 0)
+ && (arm_decode_field (given, 5, 5) == 1))
+ {
+ *unpredictable_code = UNPRED_FCA_0_FCB_1;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VPT_VEC_T4:
+ case MVE_VPT_VEC_T5:
+ case MVE_VPT_VEC_T6:
+ case MVE_VCMP_VEC_T4:
+ case MVE_VCMP_VEC_T5:
+ case MVE_VCMP_VEC_T6:
+ if (arm_decode_field (given, 0, 3) == 0xd)
+ {
+ *unpredictable_code = UNPRED_R13;
+ return TRUE;
+ }
+ else
+ return FALSE;
+
+ case MVE_VDUP:
+ {
+ unsigned long gpr = arm_decode_field (given, 12, 15);
+ if (gpr == 0xd)
+ {
+ *unpredictable_code = UNPRED_R13;
+ return TRUE;
+ }
+ else if (gpr == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+
+ return FALSE;
+ }
+
+ case MVE_VFMA_FP_SCALAR:
+ case MVE_VFMAS_FP_SCALAR:
+ case MVE_VHADD_T2:
+ case MVE_VHSUB_T2:
+ {
+ unsigned long gpr = arm_decode_field (given, 0, 3);
+ if (gpr == 0xd)
+ {
+ *unpredictable_code = UNPRED_R13;
+ return TRUE;
+ }
+ else if (gpr == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+
+ return FALSE;
+ }
+
+ case MVE_VLD2:
+ case MVE_VST2:
+ {
+ unsigned long rn = arm_decode_field (given, 16, 19);
+
+ if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
+ {
+ *unpredictable_code = UNPRED_R13_AND_WB;
+ return TRUE;
+ }
+
+ if (rn == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 6)
+ {
+ *unpredictable_code = UNPRED_Q_GT_6;
+ return TRUE;
+ }
+ else
+ return FALSE;
+ }
+
+ case MVE_VLD4:
+ case MVE_VST4:
+ {
+ unsigned long rn = arm_decode_field (given, 16, 19);
+
+ if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
+ {
+ *unpredictable_code = UNPRED_R13_AND_WB;
+ return TRUE;
+ }
+
+ if (rn == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+
+ if (arm_decode_field_multiple (given, 13, 15, 22, 22) > 4)
+ {
+ *unpredictable_code = UNPRED_Q_GT_4;
+ return TRUE;
+ }
+ else
+ return FALSE;
+ }
+
+ case MVE_VLDRB_T5:
+ case MVE_VLDRH_T6:
+ case MVE_VLDRW_T7:
+ case MVE_VSTRB_T5:
+ case MVE_VSTRH_T6:
+ case MVE_VSTRW_T7:
+ {
+ unsigned long rn = arm_decode_field (given, 16, 19);
+
+ if ((rn == 0xd) && (arm_decode_field (given, 21, 21) == 1))
+ {
+ *unpredictable_code = UNPRED_R13_AND_WB;
+ return TRUE;
+ }
+ else if (rn == 0xf)
+ {
+ *unpredictable_code = UNPRED_R15;
+ return TRUE;
+ }
+ else
+ return FALSE;
+ }
+
+ default:
+ return FALSE;
+ }
+}
+
+static void
+print_mve_undefined (struct disassemble_info *info,
+ enum mve_undefined undefined_code)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ func (stream, "\t\tundefined instruction: ");
+
+ switch (undefined_code)
+ {
+ case UNDEF_SIZE_0:
+ func (stream, "size equals zero");
+ break;
+
+ case UNDEF_SIZE_3:
+ func (stream, "size equals three");
+ break;
+
+ case UNDEF_SIZE_LE_1:
+ func (stream, "size <= 1");
+ break;
+
+ case UNDEF_NONE:
+ break;
+ }
+
+}
+
+static void
+print_mve_unpredictable (struct disassemble_info *info,
+ enum mve_unpredictable unpredict_code)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
+
+ switch (unpredict_code)
+ {
+ case UNPRED_IT_BLOCK:
+ func (stream, "mve instruction in it block");
+ break;
+
+ case UNPRED_FCA_0_FCB_1:
+ func (stream, "condition bits, fca = 0 and fcb = 1");
+ break;
+
+ case UNPRED_R13:
+ func (stream, "use of r13 (sp)");
+ break;
+
+ case UNPRED_R15:
+ func (stream, "use of r15 (pc)");
+ break;
+
+ case UNPRED_Q_GT_4:
+ func (stream, "start register block > r4");
+ break;
+
+ case UNPRED_Q_GT_6:
+ func (stream, "start register block > r6");
+ break;
+
+ case UNPRED_R13_AND_WB:
+ func (stream, "use of r13 and write back");
+ break;
+
+ case UNPRED_NONE:
+ break;
+ }
+}
+
+/* Print register block operand for mve vld2/vld4/vst2/vld4. */
+
+static void
+print_mve_register_blocks (struct disassemble_info *info,
+ unsigned long given,
+ enum mve_instructions matched_insn)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ unsigned long q_reg_start = arm_decode_field_multiple (given,
+ 13, 15,
+ 22, 22);
+ switch (matched_insn)
+ {
+ case MVE_VLD2:
+ case MVE_VST2:
+ if (q_reg_start <= 6)
+ func (stream, "{q%ld, q%ld}", q_reg_start, q_reg_start + 1);
+ else
+ func (stream, "<illegal reg q%ld>", q_reg_start);
+ break;
+
+ case MVE_VLD4:
+ case MVE_VST4:
+ if (q_reg_start <= 4)
+ func (stream, "{q%ld, q%ld, q%ld, q%ld}", q_reg_start,
+ q_reg_start + 1, q_reg_start + 2,
+ q_reg_start + 3);
+ else
+ func (stream, "<illegal reg q%ld>", q_reg_start);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void
+print_instruction_predicate (struct disassemble_info *info)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ if (vpt_block_state.next_pred_state == PRED_THEN)
+ func (stream, "t");
+ else if (vpt_block_state.next_pred_state == PRED_ELSE)
+ func (stream, "e");
+}
+
+static void
+print_mve_size (struct disassemble_info *info,
+ unsigned long size,
+ enum mve_instructions matched_insn)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ switch (matched_insn)
+ {
+ case MVE_VCMP_VEC_T1:
+ case MVE_VCMP_VEC_T2:
+ case MVE_VCMP_VEC_T3:
+ case MVE_VCMP_VEC_T4:
+ case MVE_VCMP_VEC_T5:
+ case MVE_VCMP_VEC_T6:
+ case MVE_VHADD_T1:
+ case MVE_VHADD_T2:
+ case MVE_VHSUB_T1:
+ case MVE_VHSUB_T2:
+ case MVE_VLD2:
+ case MVE_VLD4:
+ case MVE_VLDRB_T1:
+ case MVE_VLDRH_T2:
+ case MVE_VPT_VEC_T1:
+ case MVE_VPT_VEC_T2:
+ case MVE_VPT_VEC_T3:
+ case MVE_VPT_VEC_T4:
+ case MVE_VPT_VEC_T5:
+ case MVE_VPT_VEC_T6:
+ case MVE_VRHADD:
+ case MVE_VST2:
+ case MVE_VST4:
+ case MVE_VSTRB_T1:
+ case MVE_VSTRH_T2:
+ if (size <= 3)
+ func (stream, "%s", mve_vec_sizename[size]);
+ else
+ func (stream, "<undef size>");
+ break;
+
+ case MVE_VCMP_FP_T1:
+ case MVE_VCMP_FP_T2:
+ case MVE_VFMA_FP_SCALAR:
+ case MVE_VFMA_FP:
+ case MVE_VFMS_FP:
+ case MVE_VFMAS_FP_SCALAR:
+ case MVE_VPT_FP_T1:
+ case MVE_VPT_FP_T2:
+ if (size == 0)
+ func (stream, "32");
+ else if (size == 1)
+ func (stream, "16");
+ break;
+
+ case MVE_VDUP:
+ switch (size)
+ {
+ case 0:
+ func (stream, "32");
+ break;
+ case 1:
+ func (stream, "16");
+ break;
+ case 2:
+ func (stream, "8");
+ break;
+ default:
+ break;
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void
+print_vec_condition (struct disassemble_info *info, long given,
+ enum mve_instructions matched_insn)
+{
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+ long vec_cond = 0;
+
+ switch (matched_insn)
+ {
+ case MVE_VPT_FP_T1:
+ case MVE_VCMP_FP_T1:
+ vec_cond = (((given & 0x1000) >> 10)
+ | ((given & 1) << 1)
+ | ((given & 0x0080) >> 7));
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_FP_T2:
+ case MVE_VCMP_FP_T2:
+ vec_cond = (((given & 0x1000) >> 10)
+ | ((given & 0x0020) >> 4)
+ | ((given & 0x0080) >> 7));
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T1:
+ case MVE_VCMP_VEC_T1:
+ vec_cond = (given & 0x0080) >> 7;
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T2:
+ case MVE_VCMP_VEC_T2:
+ vec_cond = 2 | ((given & 0x0080) >> 7);
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T3:
+ case MVE_VCMP_VEC_T3:
+ vec_cond = 4 | ((given & 1) << 1) | ((given & 0x0080) >> 7);
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T4:
+ case MVE_VCMP_VEC_T4:
+ vec_cond = (given & 0x0080) >> 7;
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T5:
+ case MVE_VCMP_VEC_T5:
+ vec_cond = 2 | ((given & 0x0080) >> 7);
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_VPT_VEC_T6:
+ case MVE_VCMP_VEC_T6:
+ vec_cond = 4 | ((given & 0x0020) >> 4) | ((given & 0x0080) >> 7);
+ func (stream, "%s",vec_condnames[vec_cond]);
+ break;
+
+ case MVE_NONE:
+ case MVE_VPST:
+ default:
+ break;
+ }
+}
+
+#define W_BIT 21
+#define I_BIT 22
+#define U_BIT 23
+#define P_BIT 24
+
+#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
+#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
+#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
+#define PRE_BIT_SET (given & (1 << P_BIT))
+
+
+/* Print one coprocessor instruction on INFO->STREAM.
+ Return TRUE if the instuction matched, FALSE if this is not a
+ recognised coprocessor instruction. */
+
+static bfd_boolean
+print_insn_coprocessor (bfd_vma pc,
+ struct disassemble_info *info,
+ long given,
+ bfd_boolean thumb)
+{
+ const struct sopcode32 *insn;
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+ unsigned long mask;
+ unsigned long value = 0;
+ int cond;
+ int cp_num;
+ struct arm_private_data *private_data = info->private_data;
+ arm_feature_set allowed_arches = ARM_ARCH_NONE;
+ arm_feature_set arm_ext_v8_1m_main =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
+
+ allowed_arches = private_data->features;
+
+ for (insn = coprocessor_opcodes; insn->assembler; insn++)
+ {
+ unsigned long u_reg = 16;
+ bfd_boolean is_unpredictable = FALSE;
+ signed long value_in_comment = 0;
+ const char *c;
+
+ if (ARM_FEATURE_ZERO (insn->arch))
+ switch (insn->value)
+ {
+ case SENTINEL_IWMMXT_START:
+ if (info->mach != bfd_mach_arm_XScale
+ && info->mach != bfd_mach_arm_iWMMXt
+ && info->mach != bfd_mach_arm_iWMMXt2)
+ do
+ insn++;
+ while ((! ARM_FEATURE_ZERO (insn->arch))
+ && insn->value != SENTINEL_IWMMXT_END);
+ continue;
+
+ case SENTINEL_IWMMXT_END:
+ continue;
+
+ case SENTINEL_GENERIC_START:
+ allowed_arches = private_data->features;
+ continue;
+
+ default:
+ abort ();
+ }
+
+ mask = insn->mask;
+ value = insn->value;
+ cp_num = (given >> 8) & 0xf;
+
+ if (thumb)
+ {
+ /* The high 4 bits are 0xe for Arm conditional instructions, and
+ 0xe for arm unconditional instructions. The rest of the
+ encoding is the same. */
mask |= 0xf0000000;
value |= 0xe0000000;
if (ifthen_state)
}
}
+ if ((insn->isa == T32 && !thumb)
+ || (insn->isa == ARM && thumb))
+ continue;
+
if ((given & mask) != value)
continue;
{
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
is_unpredictable = TRUE;
+
+ /* Armv8.1-M Mainline FP & MVE instructions. */
+ if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
+ && !ARM_CPU_IS_ANY (allowed_arches)
+ && (cp_num == 8 || cp_num == 14 || cp_num == 15))
+ continue;
+
}
else if (insn->value == 0x0e000000 /* cdp */
|| insn->value == 0xfe000000 /* cdp2 */
/* Floating-point instructions. */
if (cp_num == 9 || cp_num == 10 || cp_num == 11)
continue;
+
+ /* Armv8.1-M Mainline FP & MVE instructions. */
+ if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
+ && !ARM_CPU_IS_ANY (allowed_arches)
+ && (cp_num == 8 || cp_num == 14 || cp_num == 15))
+ continue;
}
+ else if ((insn->value == 0xec100f80 /* vldr (system register) */
+ || insn->value == 0xec000f80) /* vstr (system register) */
+ && arm_decode_field (given, 24, 24) == 0
+ && arm_decode_field (given, 21, 21) == 0)
+ /* If the P and W bits are both 0 then these encodings match the MVE
+ VLDR and VSTR instructions, these are in a different table, so we
+ don't let it match here. */
+ continue;
+
for (c = insn->assembler; *c; c++)
{
if (*c == '%')
{
- switch (*++c)
+ const char mod = *++c;
+ switch (mod)
{
case '%':
func (stream, "%%");
break;
case 'A':
+ case 'K':
{
int rn = (given >> 16) & 0xf;
bfd_vma offset = given & 0xff;
+ if (mod == 'K')
+ offset = given & 0x7f;
+
func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
if (PRE_BIT_SET || WRITEBACK_BIT_SET)
info->print_address_func (offset + pc
+ info->bytes_per_chunk * 2
- (pc & 3),
- info);
+ info);
}
}
break;
}
break;
+ case 'C':
+ {
+ bfd_boolean single = ((given >> 8) & 1) == 0;
+ char reg_prefix = single ? 's' : 'd';
+ int Dreg = (given >> 22) & 0x1;
+ int Vdreg = (given >> 12) & 0xf;
+ int reg = single ? ((Vdreg << 1) | Dreg)
+ : ((Dreg << 4) | Vdreg);
+ int num = (given >> (single ? 0 : 1)) & 0x7f;
+ int maxreg = single ? 31 : 15;
+ int topreg = reg + num - 1;
+
+ if (!num)
+ func (stream, "{VPR}");
+ else if (num == 1)
+ func (stream, "{%c%d, VPR}", reg_prefix, reg);
+ else if (topreg > maxreg)
+ func (stream, "{%c%d-<overflow reg d%d, VPR}",
+ reg_prefix, reg, single ? topreg >> 1 : topreg);
+ else
+ func (stream, "{%c%d-%c%d, VPR}", reg_prefix, reg,
+ reg_prefix, topreg);
+ }
+ break;
+
case 'u':
if (cond != COND_UNCOND)
is_unpredictable = TRUE;
break;
+ case 'J':
+ {
+ unsigned long regno
+ = arm_decode_field_multiple (given, 13, 15, 22, 22);
+
+ switch (regno)
+ {
+ case 0x1:
+ func (stream, "FPSCR");
+ break;
+ case 0x2:
+ func (stream, "FPSCR_nzcvqc");
+ break;
+ case 0xc:
+ func (stream, "VPR");
+ break;
+ case 0xd:
+ func (stream, "P0");
+ break;
+ case 0xe:
+ func (stream, "FPCXTNS");
+ break;
+ case 0xf:
+ func (stream, "FPCXTS");
+ break;
+ default:
+ func (stream, "<invalid reg %lu>", regno);
+ break;
+ }
+ }
+ break;
+
case 'F':
switch (given & 0x00408000)
{
default:
abort ();
}
- break;
+ }
+ break;
- case 'y':
- case 'z':
- {
- int single = *c++ == 'y';
- int regno;
+ case 'y':
+ case 'z':
+ {
+ int single = *c++ == 'y';
+ int regno;
- switch (*c)
- {
- case '4': /* Sm pair */
- case '0': /* Sm, Dm */
- regno = given & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 5) & 1;
- }
- else
- regno += ((given >> 5) & 1) << 4;
- break;
+ switch (*c)
+ {
+ case '4': /* Sm pair */
+ case '0': /* Sm, Dm */
+ regno = given & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 5) & 1;
+ }
+ else
+ regno += ((given >> 5) & 1) << 4;
+ break;
- case '1': /* Sd, Dd */
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
+ case '1': /* Sd, Dd */
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ else
+ regno += ((given >> 22) & 1) << 4;
+ break;
- case '2': /* Sn, Dn */
- regno = (given >> 16) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 7) & 1;
- }
- else
- regno += ((given >> 7) & 1) << 4;
- break;
+ case '2': /* Sn, Dn */
+ regno = (given >> 16) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 7) & 1;
+ }
+ else
+ regno += ((given >> 7) & 1) << 4;
+ break;
- case '3': /* List */
- func (stream, "{");
- regno = (given >> 12) & 0x0000000f;
- if (single)
- {
- regno <<= 1;
- regno += (given >> 22) & 1;
- }
- else
- regno += ((given >> 22) & 1) << 4;
- break;
+ case '3': /* List */
+ func (stream, "{");
+ regno = (given >> 12) & 0x0000000f;
+ if (single)
+ {
+ regno <<= 1;
+ regno += (given >> 22) & 1;
+ }
+ else
+ regno += ((given >> 22) & 1) << 4;
+ break;
- default:
- abort ();
- }
+ default:
+ abort ();
+ }
- func (stream, "%c%d", single ? 's' : 'd', regno);
+ func (stream, "%c%d", single ? 's' : 'd', regno);
- if (*c == '3')
- {
- int count = given & 0xff;
+ if (*c == '3')
+ {
+ int count = given & 0xff;
- if (single == 0)
- count >>= 1;
+ if (single == 0)
+ count >>= 1;
- if (--count)
- {
- func (stream, "-%c%d",
- single ? 's' : 'd',
- regno + count);
- }
+ if (--count)
+ {
+ func (stream, "-%c%d",
+ single ? 's' : 'd',
+ regno + count);
+ }
+
+ func (stream, "}");
+ }
+ else if (*c == '4')
+ func (stream, ", %c%d", single ? 's' : 'd',
+ regno + 1);
+ }
+ break;
+
+ case 'L':
+ switch (given & 0x00400100)
+ {
+ case 0x00000000: func (stream, "b"); break;
+ case 0x00400000: func (stream, "h"); break;
+ case 0x00000100: func (stream, "w"); break;
+ case 0x00400100: func (stream, "d"); break;
+ default:
+ break;
+ }
+ break;
+
+ case 'Z':
+ {
+ /* given (20, 23) | given (0, 3) */
+ value = ((given >> 16) & 0xf0) | (given & 0xf);
+ func (stream, "%d", (int) value);
+ }
+ break;
+
+ case 'l':
+ /* This is like the 'A' operator, except that if
+ the width field "M" is zero, then the offset is
+ *not* multiplied by four. */
+ {
+ int offset = given & 0xff;
+ int multiplier = (given & 0x00000100) ? 4 : 1;
+
+ func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
+
+ if (multiplier > 1)
+ {
+ value_in_comment = offset * multiplier;
+ if (NEGATIVE_BIT_SET)
+ value_in_comment = - value_in_comment;
+ }
+
+ if (offset)
+ {
+ if (PRE_BIT_SET)
+ func (stream, ", #%s%d]%s",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier,
+ WRITEBACK_BIT_SET ? "!" : "");
+ else
+ func (stream, "], #%s%d",
+ NEGATIVE_BIT_SET ? "-" : "",
+ offset * multiplier);
+ }
+ else
+ func (stream, "]");
+ }
+ break;
- func (stream, "}");
- }
- else if (*c == '4')
- func (stream, ", %c%d", single ? 's' : 'd',
- regno + 1);
- }
- break;
+ case 'r':
+ {
+ int imm4 = (given >> 4) & 0xf;
+ int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
+ int ubit = ! NEGATIVE_BIT_SET;
+ const char *rm = arm_regnames [given & 0xf];
+ const char *rn = arm_regnames [(given >> 16) & 0xf];
- case 'L':
- switch (given & 0x00400100)
+ switch (puw_bits)
{
- case 0x00000000: func (stream, "b"); break;
- case 0x00400000: func (stream, "h"); break;
- case 0x00000100: func (stream, "w"); break;
- case 0x00400100: func (stream, "d"); break;
- default:
+ case 1:
+ case 3:
+ func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
+ if (imm4)
+ func (stream, ", lsl #%d", imm4);
break;
- }
- break;
-
- case 'Z':
- {
- /* given (20, 23) | given (0, 3) */
- value = ((given >> 16) & 0xf0) | (given & 0xf);
- func (stream, "%d", (int) value);
- }
- break;
-
- case 'l':
- /* This is like the 'A' operator, except that if
- the width field "M" is zero, then the offset is
- *not* multiplied by four. */
- {
- int offset = given & 0xff;
- int multiplier = (given & 0x00000100) ? 4 : 1;
-
- func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
-
- if (multiplier > 1)
- {
- value_in_comment = offset * multiplier;
- if (NEGATIVE_BIT_SET)
- value_in_comment = - value_in_comment;
- }
- if (offset)
- {
- if (PRE_BIT_SET)
- func (stream, ", #%s%d]%s",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier,
- WRITEBACK_BIT_SET ? "!" : "");
- else
- func (stream, "], #%s%d",
- NEGATIVE_BIT_SET ? "-" : "",
- offset * multiplier);
- }
- else
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
+ if (imm4 > 0)
+ func (stream, ", lsl #%d", imm4);
func (stream, "]");
- }
- break;
-
- case 'r':
- {
- int imm4 = (given >> 4) & 0xf;
- int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
- int ubit = ! NEGATIVE_BIT_SET;
- const char *rm = arm_regnames [given & 0xf];
- const char *rn = arm_regnames [(given >> 16) & 0xf];
-
- switch (puw_bits)
- {
- case 1:
- case 3:
- func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4)
- func (stream, ", lsl #%d", imm4);
- break;
-
- case 4:
- case 5:
- case 6:
- case 7:
- func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
- if (imm4 > 0)
- func (stream, ", lsl #%d", imm4);
- func (stream, "]");
- if (puw_bits == 5 || puw_bits == 7)
- func (stream, "!");
- break;
-
- default:
- func (stream, "INVALID");
- }
- }
- break;
+ if (puw_bits == 5 || puw_bits == 7)
+ func (stream, "!");
+ break;
- case 'i':
- {
- long imm5;
- imm5 = ((given & 0x100) >> 4) | (given & 0xf);
- func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
- }
- break;
+ default:
+ func (stream, "INVALID");
+ }
+ }
+ break;
- default:
- abort ();
+ case 'i':
+ {
+ long imm5;
+ imm5 = ((given & 0x100) >> 4) | (given & 0xf);
+ func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
}
+ break;
+
+ default:
+ abort ();
}
}
else
}
else if ((given & 0xff000000) == 0xf9000000)
given ^= 0xf9000000 ^ 0xf4000000;
- else
+ /* vdup is also a valid neon instruction. */
+ else if ((given & 0xff910f5f) != 0xee800b10)
return FALSE;
}
default:
abort ();
}
- break;
+ }
+ break;
+
+ default:
+ abort ();
+ }
+ }
+ else
+ func (stream, "%c", *c);
+ }
+
+ if (value_in_comment > 32 || value_in_comment < -16)
+ func (stream, "\t; 0x%lx", value_in_comment);
+
+ if (is_unpredictable)
+ func (stream, UNPREDICTABLE_INSTRUCTION);
+
+ return TRUE;
+ }
+ }
+ return FALSE;
+}
+
+/* Print one mve instruction on INFO->STREAM.
+ Return TRUE if the instuction matched, FALSE if this is not a
+ recognised mve instruction. */
+
+static bfd_boolean
+print_insn_mve (struct disassemble_info *info, long given)
+{
+ const struct mopcode32 *insn;
+ void *stream = info->stream;
+ fprintf_ftype func = info->fprintf_func;
+
+ for (insn = mve_opcodes; insn->assembler; insn++)
+ {
+ if (((given & insn->mask) == insn->value)
+ && !is_mve_encoding_conflict (given, insn->mve_op))
+ {
+ signed long value_in_comment = 0;
+ bfd_boolean is_unpredictable = FALSE;
+ bfd_boolean is_undefined = FALSE;
+ const char *c;
+ enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
+ enum mve_undefined undefined_cond = UNDEF_NONE;
+
+ /* Most vector mve instruction are illegal in a it block.
+ There are a few exceptions; check for them. */
+ if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
+ {
+ is_unpredictable = TRUE;
+ unpredictable_cond = UNPRED_IT_BLOCK;
+ }
+ else if (is_mve_unpredictable (given, insn->mve_op,
+ &unpredictable_cond))
+ is_unpredictable = TRUE;
+
+ if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
+ is_undefined = TRUE;
+
+ for (c = insn->assembler; *c; c++)
+ {
+ if (*c == '%')
+ {
+ switch (*++c)
+ {
+ case '%':
+ func (stream, "%%");
+ break;
+
+ case 'c':
+ if (ifthen_state)
+ func (stream, "%s", arm_conditional[IFTHEN_COND]);
+ break;
+
+ case 'd':
+ print_mve_vld_str_addr (info, given, insn->mve_op);
+ break;
+
+ case 'i':
+ {
+ long mve_mask = mve_extract_pred_mask (given);
+ func (stream, "%s", mve_predicatenames[mve_mask]);
+ }
+ break;
+
+ case 'n':
+ print_vec_condition (info, given, insn->mve_op);
+ break;
+
+ case 'u':
+ {
+ if (arm_decode_field (given, 28, 28) == 0)
+ func (stream, "s");
+ else
+ func (stream, "u");
+ }
+
+ case 'v':
+ print_instruction_predicate (info);
+ break;
+
+ case 'w':
+ if (arm_decode_field (given, 21, 21) == 1)
+ func (stream, "!");
+ break;
+
+ case 'B':
+ print_mve_register_blocks (info, given, insn->mve_op);
+ break;
+
+ case '0': case '1': case '2': case '3': case '4':
+ case '5': case '6': case '7': case '8': case '9':
+ {
+ int width;
+ unsigned long value;
+
+ c = arm_decode_bitfield (c, given, &value, &width);
+ switch (*c)
+ {
+ case 'Z':
+ if (value == 13)
+ is_unpredictable = TRUE;
+ else if (value == 15)
+ func (stream, "zr");
+ else
+ func (stream, "%s", arm_regnames[value]);
+ break;
+ case 's':
+ print_mve_size (info,
+ value,
+ insn->mve_op);
+ break;
+ case 'r':
+ func (stream, "%s", arm_regnames[value]);
+ break;
+ case 'd':
+ func (stream, "%ld", value);
+ value_in_comment = value;
+ break;
+ case 'Q':
+ if (value & 0x8)
+ func (stream, "<illegal reg q%ld.5>", value);
+ else
+ func (stream, "q%ld", value);
+ break;
+ default:
+ abort ();
+ }
+ break;
default:
abort ();
}
func (stream, "\t; 0x%lx", value_in_comment);
if (is_unpredictable)
- func (stream, UNPREDICTABLE_INSTRUCTION);
+ print_mve_unpredictable (info, unpredictable_cond);
+
+ if (is_undefined)
+ print_mve_undefined (info, undefined_cond);
+
+ if ((vpt_block_state.in_vpt_block == FALSE)
+ && !ifthen_state
+ && (is_vpt_instruction (given) == TRUE))
+ mark_inside_vpt_block (given);
+ else if (vpt_block_state.in_vpt_block == TRUE)
+ update_vpt_block_state ();
return TRUE;
}
return FALSE;
}
+
/* Return the name of a v7A special register. */
static const char *
default:
abort ();
}
- break;
-
- case 'e':
- {
- int imm;
+ }
+ break;
- imm = (given & 0xf) | ((given & 0xfff00) >> 4);
- func (stream, "%d", imm);
- value_in_comment = imm;
- }
- break;
+ case 'e':
+ {
+ int imm;
- case 'E':
- /* LSB and WIDTH fields of BFI or BFC. The machine-
- language instruction encodes LSB and MSB. */
- {
- long msb = (given & 0x001f0000) >> 16;
- long lsb = (given & 0x00000f80) >> 7;
- long w = msb - lsb + 1;
+ imm = (given & 0xf) | ((given & 0xfff00) >> 4);
+ func (stream, "%d", imm);
+ value_in_comment = imm;
+ }
+ break;
- if (w > 0)
- func (stream, "#%lu, #%lu", lsb, w);
- else
- func (stream, "(invalid: %lu:%lu)", lsb, msb);
- }
- break;
+ case 'E':
+ /* LSB and WIDTH fields of BFI or BFC. The machine-
+ language instruction encodes LSB and MSB. */
+ {
+ long msb = (given & 0x001f0000) >> 16;
+ long lsb = (given & 0x00000f80) >> 7;
+ long w = msb - lsb + 1;
- case 'R':
- /* Get the PSR/banked register name. */
- {
- const char * name;
- unsigned sysm = (given & 0x004f0000) >> 16;
+ if (w > 0)
+ func (stream, "#%lu, #%lu", lsb, w);
+ else
+ func (stream, "(invalid: %lu:%lu)", lsb, msb);
+ }
+ break;
- sysm |= (given & 0x300) >> 4;
- name = banked_regname (sysm);
+ case 'R':
+ /* Get the PSR/banked register name. */
+ {
+ const char * name;
+ unsigned sysm = (given & 0x004f0000) >> 16;
- if (name != NULL)
- func (stream, "%s", name);
- else
- func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
- }
- break;
+ sysm |= (given & 0x300) >> 4;
+ name = banked_regname (sysm);
- case 'V':
- /* 16-bit unsigned immediate from a MOVT or MOVW
- instruction, encoded in bits 0:11 and 15:19. */
- {
- long hi = (given & 0x000f0000) >> 4;
- long lo = (given & 0x00000fff);
- long imm16 = hi | lo;
+ if (name != NULL)
+ func (stream, "%s", name);
+ else
+ func (stream, "(UNDEF: %lu)", (unsigned long) sysm);
+ }
+ break;
- func (stream, "#%lu", imm16);
- value_in_comment = imm16;
- }
- break;
+ case 'V':
+ /* 16-bit unsigned immediate from a MOVT or MOVW
+ instruction, encoded in bits 0:11 and 15:19. */
+ {
+ long hi = (given & 0x000f0000) >> 4;
+ long lo = (given & 0x00000fff);
+ long imm16 = hi | lo;
- default:
- abort ();
+ func (stream, "#%lu", imm16);
+ value_in_comment = imm16;
}
+ break;
+
+ default:
+ abort ();
}
}
else
mask. */
if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
func (stream, "!");
- break;
+ break;
case 'b':
/* Print ARM V6T2 CZB address: pc+4+6 bits. */
const struct opcode32 *insn;
void *stream = info->stream;
fprintf_ftype func = info->fprintf_func;
+ bfd_boolean is_mve = is_mve_architecture (info);
if (print_insn_coprocessor (pc, info, given, TRUE))
return;
- if (print_insn_neon (info, given, TRUE))
+ if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
+ return;
+
+ if (is_mve && print_insn_mve (info, given))
return;
for (insn = thumb32_opcodes; insn->assembler; insn++)
if ((given & insn->mask) == insn->value)
{
+ bfd_boolean is_clrm = FALSE;
bfd_boolean is_unpredictable = FALSE;
signed long value_in_comment = 0;
const char *c = insn->assembler;
}
break;
+ case 'n':
+ is_clrm = TRUE;
+ /* Fall through. */
case 'm':
{
int started = 0;
if (started)
func (stream, ", ");
started = 1;
- func (stream, "%s", arm_regnames[reg]);
+ if (is_clrm && reg == 13)
+ func (stream, "(invalid: %s)", arm_regnames[reg]);
+ else if (is_clrm && reg == 15)
+ func (stream, "%s", "APSR");
+ else
+ func (stream, "%s", arm_regnames[reg]);
}
func (stream, "}");
}
}
break;
+ case 'G':
+ {
+ unsigned int boff = (((given & 0x07800000) >> 23) << 1);
+ func (stream, "%x", boff);
+ }
+ break;
+
+ case 'W':
+ {
+ unsigned int immA = (given & 0x001f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x10000) ? offset - (1 << 17) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
+ case 'Y':
+ {
+ unsigned int immA = (given & 0x007f0000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x40000) ? offset - (1 << 19) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+ }
+ break;
+
+ case 'Z':
+ {
+ unsigned int immA = (given & 0x00010000u) >> 16;
+ unsigned int immB = (given & 0x000007feu) >> 1;
+ unsigned int immC = (given & 0x00000800u) >> 11;
+ bfd_vma offset = 0;
+
+ offset |= immA << 12;
+ offset |= immB << 2;
+ offset |= immC << 1;
+ /* Sign extend. */
+ offset = (offset & 0x1000) ? offset - (1 << 13) : offset;
+
+ info->print_address_func (pc + 4 + offset, info);
+
+ unsigned int T = (given & 0x00020000u) >> 17;
+ unsigned int endoffset = (((given & 0x07800000) >> 23) << 1);
+ unsigned int boffset = (T == 1) ? 4 : 2;
+ func (stream, ", ");
+ func (stream, "%x", endoffset + boffset);
+ }
+ break;
+
+ case 'Q':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 + imm32, info);
+ }
+ break;
+
+ case 'P':
+ {
+ unsigned int immh = (given & 0x000007feu) >> 1;
+ unsigned int imml = (given & 0x00000800u) >> 11;
+ bfd_vma imm32 = 0;
+
+ imm32 |= immh << 2;
+ imm32 |= imml << 1;
+
+ info->print_address_func (pc + 4 - imm32, info);
+ }
+ break;
+
case 'b':
{
unsigned int S = (given & 0x04000000u) >> 26;
value_in_comment = val * 4;
break;
+ case 'S':
+ if (val == 13)
+ is_unpredictable = TRUE;
+ /* Fall through. */
case 'R':
if (val == 15)
is_unpredictable = TRUE;
case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
+ case bfd_mach_arm_8_1M_MAIN:
+ ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
+ force_thumb = 1;
+ break;
/* If the machine type is unknown allow all architecture types and all
extensions. */
case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;