Make the objfile destructor private

[deliverable/binutils-gdb.git] / opcodes / arm-dis.c

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index 8f82cb24e46defbfe5963237a6b5a2cc94adb258..f6937584e8bc57501e5cd0dca147f05b8e53429e 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -2842,10 +2842,15 @@ static const struct mopcode32 mve_opcodes[] =
    "vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
 
   /* Vector VMOV immediate to vector,
-     cmode == 11x1 -> VMVN which is UNDEFINED
-     for such a cmode.  */
+     undefinded for cmode == 1111 */
   {ARM_FEATURE_COPROC (FPU_MVE),
-   MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
+   MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
+
+  /* Vector VMOV immediate to vector,
+     cmode == 1101 */
+  {ARM_FEATURE_COPROC (FPU_MVE),
+   MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
+   "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
 
   /* Vector VMOV immediate to vector.  */
   {ARM_FEATURE_COPROC (FPU_MVE),
@@ -3636,17 +3641,17 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
     0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
   /* CRC32 instructions.  */
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
 
   /* Privileged Access Never extension instructions.  */
@@ -4652,17 +4657,17 @@ static const struct opcode32 thumb32_opcodes[] =
     0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
 
   /* CRC32 instructions.  */
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
-  {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+  {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
     0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
 
   /* Speculation Barriers.  */
@@ -5664,11 +5669,11 @@ is_mve_encoding_conflict (unsigned long given,
       {
        unsigned long cmode = arm_decode_field (given, 8, 11);
 
-       if ((cmode & 9) == 1)
+       if (cmode == 0xe)
          return TRUE;
-       else if ((cmode & 5) == 1)
+       else if ((cmode & 0x9) == 1)
          return TRUE;
-       else if ((cmode & 0xe) == 0xe)
+       else if ((cmode & 0xd) == 9)
          return TRUE;
        else
          return FALSE;