{ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16),
0xfe300810, 0xffb00f10, "vfma%6?tb.bf16\t%12-15,22Q, %16-19,7Q, %0-2D[%3,5d]"},
+ /* Matrix Multiply instructions. */
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfc200c40, 0xffb00f50, "vsmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfc200c50, 0xffb00f50, "vummla.u8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfca00c40, 0xffb00f50, "vusmmla.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfca00d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfe800d00, 0xffb00f10, "vusdot.s8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM),
+ 0xfe800d10, 0xffb00f10, "vsudot.u8\t%12-15,22R, %16-19,7R, d%0-3d[%5d]"},
+
/* Two registers, miscellaneous. */
{ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8),
0xf3ba0400, 0xffbf0c10, "vrint%7-9?p?m?zaxn%u.f32\t%12-15,22R, %0-3,5R"},
"vsri%v.%19-21s\t%13-15,22Q, %1-3,5Q, #%16-18d"},
/* Vector VMOV immediate to vector,
- cmode == 11x1 -> VMVN which is UNDEFINED
- for such a cmode. */
+ undefinded for cmode == 1111 */
{ARM_FEATURE_COPROC (FPU_MVE),
- MVE_VMVN_IMM, 0xef800d50, 0xefb81dd0, UNDEFINED_INSTRUCTION},
+ MVE_VMVN_IMM, 0xef800f70, 0xefb81ff0, UNDEFINED_INSTRUCTION},
+
+ /* Vector VMOV immediate to vector,
+ cmode == 1101 */
+ {ARM_FEATURE_COPROC (FPU_MVE),
+ MVE_VMOV_IMM_TO_VEC, 0xef800d50, 0xefb81fd0,
+ "vmov%v.%5,8-11s\t%13-15,22Q, %E"},
/* Vector VMOV immediate to vector. */
{ARM_FEATURE_COPROC (FPU_MVE),
{ARM_FEATURE_CORE_LOW (ARM_EXT2_ATOMICS),
0x01f00c9f, 0x0ff00fff, "ldah%c\t%12-15r, [%16-19R]"},
/* CRC32 instructions. */
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1000040, 0xfff00ff0, "crc32b\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1200040, 0xfff00ff0, "crc32h\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1400040, 0xfff00ff0, "crc32w\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1000240, 0xfff00ff0, "crc32cb\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1200240, 0xfff00ff0, "crc32ch\t%12-15R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xe1400240, 0xfff00ff0, "crc32cw\t%12-15R, %16-19R, %0-3R"},
/* Privileged Access Never extension instructions. */
0xe8d000ff, 0xfff000ff, "ldaexd%c\t%12-15r, %8-11r, [%16-19R]"},
/* CRC32 instructions. */
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f080, 0xfff0f0f0, "crc32b\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f090, 0xfff0f0f0, "crc32h\t%9-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfac0f0a0, 0xfff0f0f0, "crc32w\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f080, 0xfff0f0f0, "crc32cb\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f090, 0xfff0f0f0, "crc32ch\t%8-11R, %16-19R, %0-3R"},
- {ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
0xfad0f0a0, 0xfff0f0f0, "crc32cw\t%8-11R, %16-19R, %0-3R"},
/* Speculation Barriers. */
{
unsigned long cmode = arm_decode_field (given, 8, 11);
- if ((cmode & 9) == 1)
+ if (cmode == 0xe)
return TRUE;
- else if ((cmode & 5) == 1)
+ else if ((cmode & 0x9) == 1)
return TRUE;
- else if ((cmode & 0xe) == 0xe)
+ else if ((cmode & 0xd) == 9)
return TRUE;
else
return FALSE;