sim: bfin: fix UART LSR read-only bit saturation

[deliverable/binutils-gdb.git] / opcodes / bfin-dis.c

diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c
index a475c23911b8c0868fc991341cf0e547af2192d6..130dfc7719e5b4bc42517eea0a76445992ce59ba 100644 (file)
--- a/opcodes/bfin-dis.c
+++ b/opcodes/bfin-dis.c
@@ -490,7 +490,7 @@ static const enum machine_registers decode_allregs[] =
 
 /* (arch.pm)arch_disassembler_functions.  */
 #ifndef OUTS
-#define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, "%s", txt) :0) :0)
+#define OUTS(p, txt) (p)->fprintf_func ((p)->stream, "%s", txt)
 #endif
 
 static void
@@ -3010,13 +3010,16 @@ decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
        {
          if (MM)
            OUTS (outf, " (M)");
-         MM = 0;
          OUTS (outf, ", ");
        }
     }
 
   if (w0 == 1 || op0 != 3)
     {
+      /* Clear MM option since it only matters for MAC1, and if we made
+         it this far, we've already shown it or we want to ignore it.  */
+      MM = 0;
+
       if (w0)
        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
 
@@ -4781,9 +4784,9 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
       int len;
 
       parallel = 1;
-      outf->fprintf_func (outf->stream, " || ");
+      OUTS (outf, " || ");
       len = _print_insn_bfin (pc + 4, outf);
-      outf->fprintf_func (outf->stream, " || ");
+      OUTS (outf, " || ");
       if (len != 2)
        legal = 0;
       len = _print_insn_bfin (pc + 6, outf);
@@ -4794,7 +4797,7 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
        count = 8;
       else
        {
-         outf->fprintf_func (outf->stream, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
+         OUTS (outf, ";\t\t/* ILLEGAL PARALLEL INSTRUCTION */");
          comment = 1;
          count = 0;
        }
@@ -4802,7 +4805,7 @@ print_insn_bfin (bfd_vma pc, disassemble_info *outf)
     }
 
   if (!comment)
-    outf->fprintf_func (outf->stream, ";");
+    OUTS (outf, ";");
 
   if (count == 0)
     return 2;